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power.h
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1 /* Copyright (c) 2006, 2007, 2008 Eric B. Weddington
2  Copyright (c) 2011 Frédéric Nadeau
3  All rights reserved.
4 
5  Redistribution and use in source and binary forms, with or without
6  modification, are permitted provided that the following conditions are met:
7 
8  * Redistributions of source code must retain the above copyright
9  notice, this list of conditions and the following disclaimer.
10  * Redistributions in binary form must reproduce the above copyright
11  notice, this list of conditions and the following disclaimer in
12  the documentation and/or other materials provided with the
13  distribution.
14  * Neither the name of the copyright holders nor the names of
15  contributors may be used to endorse or promote products derived
16  from this software without specific prior written permission.
17 
18  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
22  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28  POSSIBILITY OF SUCH DAMAGE. */
29 
30 /* $Id: power.h 2422 2014-04-29 10:33:23Z pitchumani $ */
31 
32 #ifndef _AVR_POWER_H_
33 #define _AVR_POWER_H_ 1
34 
35 #include <avr/io.h>
36 #include <stdint.h>
37 
38 
39 /** \file */
40 /** \defgroup avr_power <avr/power.h>: Power Reduction Management
41 
42 \code #include <avr/power.h>\endcode
43 
44 Many AVRs contain a Power Reduction Register (PRR) or Registers (PRRx) that
45 allow you to reduce power consumption by disabling or enabling various on-board
46 peripherals as needed. Some devices have the XTAL Divide Control Register
47 (XDIV) which offer similar functionality as System Clock Prescale
48 Register (CLKPR).
49 
50 There are many macros in this header file that provide an easy interface
51 to enable or disable on-board peripherals to reduce power. See the table below.
52 
53 \note Not all AVR devices have a Power Reduction Register (for example
54 the ATmega8). On those devices without a Power Reduction Register, the
55 power reduction macros are not available..
56 
57 \note Not all AVR devices contain the same peripherals (for example, the LCD
58 interface), or they will be named differently (for example, USART and
59 USART0). Please consult your device's datasheet, or the header file, to
60 find out which macros are applicable to your device.
61 
62 \note For device using the XTAL Divide Control Register (XDIV), when prescaler
63 is used, Timer/Counter0 can only be used in asynchronous mode. Keep in mind
64 that Timer/Counter0 source shall be less than ¼th of peripheral clock.
65 Therefore, when using a typical 32.768 kHz crystal, one shall not scale
66 the clock below 131.072 kHz.
67 
68 */
69 
70 
71 /** \addtogroup avr_power
72 
73 \anchor avr_powermacros
74 <small>
75 <center>
76 <table border="3">
77  <tr>
78  <td width="10%"><strong>Power Macro</strong></td>
79  <td width="15%"><strong>Description</strong></td>
80  <td width="75%"><strong>Applicable for device</strong></td>
81  </tr>
82 
83  <tr>
84  <td>power_aca_disable()</td>
85  <td>Disable the Analog Comparator on PortA.</td>
86  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
87  </tr>
88 
89  <tr>
90  <td>power_aca_enable()</td>
91  <td>Enable the Analog Comparator on PortA.</td>
92  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
93  </tr>
94 
95  <tr>
96  <td>power_adc_enable()</td>
97  <td>Enable the Analog to Digital Converter module.</td>
98  <td>ATmega640, ATmega1280, ATmega1281, ATmega1284, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega3290PA, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2, ATxmega16A4U, ATxmega32A4U</td>
99  </tr>
100 
101  <tr>
102  <td>power_adc_disable()</td>
103  <td>Disable the Analog to Digital Converter module.</td>
104  <td>ATmega640, ATmega1280, ATmega1281, ATmega1284, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega3290PA, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2, ATxmega16A4U, ATxmega32A4U</td>
105  </tr>
106 
107  <tr>
108  <td>power_adca_disable()</td>
109  <td>Disable the Analog to Digital Converter module on PortA</td>
110  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
111  </tr>
112 
113  <tr>
114  <td>power_adca_enable()</td>
115  <td>Enable the Analog to Digital Converter module on PortA</td>
116  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
117  </tr>
118 
119  <tr>
120  <td>power_evsys_disable()</td>
121  <td>Disable the EVSYS module</td>
122  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
123  </tr>
124 
125  <tr>
126  <td>power_evsys_enable()</td>
127  <td>Enable the EVSYS module</td>
128  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
129  </tr>
130 
131  <tr>
132  <td>power_hiresc_disable()</td>
133  <td>Disable the HIRES module on PortC</td>
134  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
135  </tr>
136 
137  <tr>
138  <td>power_hiresc_enable()</td>
139  <td>Enable the HIRES module on PortC</td>
140  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
141  </tr>
142 
143  <tr>
144  <td>power_lcd_enable()</td>
145  <td>Enable the LCD module.</td>
146  <td>ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega649, ATmega6490, ATxmega64B1, ATxmega64B3, ATxmega128B3</td>
147  </tr>
148 
149  <tr>
150  <td>power_lcd_disable().</td>
151  <td>Disable the LCD module.</td>
152  <td>ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega649, ATmega6490, ATxmega64B1, ATxmega128B1, ATxmega64B3, ATxmega128B3</td>
153  </tr>
154 
155  <tr>
156  <td>power_pga_enable()</td>
157  <td>Enable the Programmable Gain Amplifier module.</td>
158  <td> ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2</td>
159  </tr>
160 
161  <tr>
162  <td>power_pga_disable()</td>
163  <td>Disable the Programmable Gain Amplifier module.</td>
164  <td> ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2</td>
165  </tr>
166 
167  <tr>
168  <td>power_pscr_enable()</td>
169  <td>Enable the Reduced Power Stage Controller module.</td>
170  <td>AT90PWM81</td>
171  </tr>
172 
173  <tr>
174  <td>power_pscr_disable()</td>
175  <td>Disable the Reduced Power Stage Controller module.</td>
176  <td>AT90PWM81</td>
177  </tr>
178 
179  <tr>
180  <td>power_psc0_enable()</td>
181  <td>Enable the Power Stage Controller 0 module.</td>
182  <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B</td>
183  </tr>
184 
185  <tr>
186  <td>power_psc0_disable()</td>
187  <td>Disable the Power Stage Controller 0 module.</td>
188  <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B</td>
189  </tr>
190 
191  <tr>
192  <td>power_psc1_enable()</td>
193  <td>Enable the Power Stage Controller 1 module.</td>
194  <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B</td>
195  </tr>
196 
197  <tr>
198  <td>power_psc1_disable()</td>
199  <td>Disable the Power Stage Controller 1 module.</td>
200  <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B</td>
201  </tr>
202 
203  <tr>
204  <td>power_psc2_enable()</td>
205  <td>Enable the Power Stage Controller 2 module.</td>
206  <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM81</td>
207  </tr>
208 
209  <tr>
210  <td>power_psc2_disable()</td>
211  <td>Disable the Power Stage Controller 2 module.</td>
212  <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM81</td>
213  </tr>
214 
215  <tr>
216  <td>power_ram0_enable()</td>
217  <td>Enable the SRAM block 0 .</td>
218  <td> ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2</td>
219  </tr>
220 
221  <tr>
222  <td>power_ram0_disable()</td>
223  <td>Disable the SRAM block 0. </td>
224  <td> ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2</td>
225  </tr>
226 
227  <tr>
228  <td>power_ram1_enable()</td>
229  <td>Enable the SRAM block 1 .</td>
230  <td> ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2</td>
231  </tr>
232 
233  <tr>
234  <td>power_ram1_disable()</td>
235  <td>Disable the SRAM block 1. </td>
236  <td> ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2</td>
237  </tr>
238 
239  <tr>
240  <td>power_ram2_enable()</td>
241  <td>Enable the SRAM block 2 .</td>
242  <td> ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2</td>
243  </tr>
244 
245  <tr>
246  <td>power_ram2_disable()</td>
247  <td>Disable the SRAM block 2. </td>
248  <td> ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2</td>
249  </tr>
250 
251  <tr>
252  <td>power_ram3_enable()</td>
253  <td>Enable the SRAM block 3 .</td>
254  <td> ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2</td>
255  </tr>
256 
257  <tr>
258  <td>power_ram3_disable()</td>
259  <td>Disable the SRAM block 3. </td>
260  <td> ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2</td>
261  </tr>
262 
263  <tr>
264  <td>power_rtc_disable()</td>
265  <td>Disable the RTC module</td>
266  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
267  </tr>
268 
269  <tr>
270  <td>power_rtc_enable()</td>
271  <td>Enable the RTC module</td>
272  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
273  </tr>
274 
275  <tr>
276  <td>power_spi_enable()</td>
277  <td>Enable the Serial Peripheral Interface module.</td>
278  <td>ATmega640, ATmega1280, ATmega1281, ATmega1284, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega3290PA, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2, ATxmega16A4U, ATxmega32A4U</td>
279  </tr>
280 
281  <tr>
282  <td>power_spi_disable()</td>
283  <td>Disable the Serial Peripheral Interface module.</td>
284  <td>ATmega640, ATmega1280, ATmega1281, ATmega1284, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega3290PA, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2, ATxmega16A4U, ATxmega32A4U</td>
285  </tr>
286 
287  <tr>
288  <td>power_spic_disable()</td>
289  <td>Disable the SPI module on PortC</td>
290  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
291  </tr>
292 
293  <tr>
294  <td>power_spic_enable()</td>
295  <td>Enable the SPI module on PortC</td>
296  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
297  </tr>
298 
299  <tr>
300  <td>power_spid_disable()</td>
301  <td>Disable the SPI module on PortD</td>
302  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
303  </tr>
304 
305  <tr>
306  <td>power_spid_enable()</td>
307  <td>Enable the SPI module on PortD</td>
308  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
309  </tr>
310 
311  <tr>
312  <td>power_tc0c_disable()</td>
313  <td>Disable the TC0 module on PortC</td>
314  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
315  </tr>
316 
317  <tr>
318  <td>power_tc0c_enable()</td>
319  <td>Enable the TC0 module on PortC</td>
320  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
321  </tr>
322 
323  <tr>
324  <td>power_tc0d_disable()</td>
325  <td>Disable the TC0 module on PortD</td>
326  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
327  </tr>
328 
329  <tr>
330  <td>power_tc0d_enable()</td>
331  <td>Enable the TC0 module on PortD</td>
332  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
333  </tr>
334 
335  <tr>
336  <td>power_tc0e_disable()</td>
337  <td>Disable the TC0 module on PortE</td>
338  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
339  </tr>
340 
341  <tr>
342  <td>power_tc0e_enable()</td>
343  <td>Enable the TC0 module on PortE</td>
344  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
345  </tr>
346 
347  <tr>
348  <td>power_tc0f_disable()</td>
349  <td>Disable the TC0 module on PortF</td>
350  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
351  </tr>
352 
353  <tr>
354  <td>power_tc0f_enable()</td>
355  <td>Enable the TC0 module on PortF</td>
356  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
357  </tr>
358 
359  <tr>
360  <td>power_tc1c_disable()</td>
361  <td>Disable the TC1 module on PortC</td>
362  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
363  </tr>
364 
365  <tr>
366  <td>power_tc1c_enable()</td>
367  <td>Enable the TC1 module on PortC</td>
368  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
369  </tr>
370 
371  <tr>
372  <td>power_twic_disable()</td>
373  <td>Disable the Two Wire Interface module on PortC</td>
374  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
375  </tr>
376 
377  <tr>
378  <td>power_twic_enable()</td>
379  <td>Enable the Two Wire Interface module on PortC</td>
380  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
381  </tr>
382 
383  <tr>
384  <td>power_twie_disable()</td>
385  <td>Disable the Two Wire Interface module on PortE</td>
386  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
387  </tr>
388 
389  <tr>
390  <td>power_twie_enable()</td>
391  <td>Enable the Two Wire Interface module on PortE</td>
392  <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
393  </tr>
394 
395  <tr>
396  <td>power_timer0_enable()</td>
397  <td>Enable the Timer 0 module.</td>
398  <td>ATmega640, ATmega1280, ATmega1281, ATmega1284, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM216, AT90PWM316, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega3250, ATmega3250A, ATmega645, ATmega6450, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2, ATxmega16A4U, ATxmega32A4U</td>
399  </tr>
400 
401  <tr>
402  <td>power_timer0_disable()</td>
403  <td>Disable the Timer 0 module.</td>
404  <td>ATmega640, ATmega1280, ATmega1281, ATmega1284, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega3250, ATmega3250A, ATmega645, ATmega6450, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2, ATxmega16A4U, ATxmega32A4U</td>
405  </tr>
406 
407  <tr>
408  <td>power_timer1_enable()</td>
409  <td>Enable the Timer 1 module.</td>
410  <td>ATmega640, ATmega1280, ATmega1281, ATmega1284, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega3290PA, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2, ATxmega16A4U, ATxmega32A4U</td>
411  </tr>
412 
413  <tr>
414  <td>power_timer1_disable()</td>
415  <td>Disable the Timer 1 module.</td>
416  <td>ATmega640, ATmega1280, ATmega1281, ATmega1284, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega3290PA, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2, ATxmega16A4U, ATxmega32A4U</td>
417  </tr>
418 
419  <tr>
420  <td>power_timer2_enable()</td>
421  <td>Enable the Timer 2 module.</td>
422  <td>ATmega640, ATmega1280, ATmega1281, ATmega1284, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2</td>
423  </tr>
424 
425  <tr>
426  <td>power_timer2_disable()</td>
427  <td>Disable the Timer 2 module.</td>
428  <td>ATmega640, ATmega1280, ATmega1281, ATmega1284, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2</td>
429  </tr>
430 
431  <tr>
432  <td>power_timer3_enable()</td>
433  <td>Enable the Timer 3 module.</td>
434  <td>ATmega640, ATmega1280, ATmega1281, ATmega1284, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2</td>
435  </tr>
436 
437  <tr>
438  <td>power_timer3_disable()</td>
439  <td>Disable the Timer 3 module.</td>
440  <td>ATmega640, ATmega1280, ATmega1281, ATmega1284, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2</td>
441  </tr>
442 
443  <tr>
444  <td>power_timer4_enable()</td>
445  <td>Enable the Timer 4 module.</td>
446  <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2</td>
447  </tr>
448 
449  <tr>
450  <td>power_timer4_disable()</td>
451  <td>Disable the Timer 4 module.</td>
452  <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2</td>
453  </tr>
454 
455  <tr>
456  <td>power_timer5_enable()</td>
457  <td>Enable the Timer 5 module.</td>
458  <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2</td>
459  </tr>
460 
461  <tr>
462  <td>power_timer5_disable()</td>
463  <td>Disable the Timer 5 module.</td>
464  <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2</td>
465  </tr>
466 
467  <tr>
468  <td>power_twi_enable()</td>
469  <td>Enable the Two Wire Interface module.</td>
470  <td>ATmega640, ATmega1280, ATmega1281, ATmega1284, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2, ATxmega16A4U, ATxmega32A4U</td>
471  </tr>
472 
473  <tr>
474  <td>power_twi_disable()</td>
475  <td>Disable the Two Wire Interface module.</td>
476  <td>ATmega640, ATmega1280, ATmega1281, ATmega1284, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2, ATxmega16A4U, ATxmega32A4U</td>
477  </tr>
478 
479  <tr>
480  <td>power_usart_enable()</td>
481  <td>Enable the USART module.</td>
482  <td>AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B</td>
483  </tr>
484 
485  <tr>
486  <td>power_usart_disable()</td>
487  <td>Disable the USART module.</td>
488  <td>AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B</td>
489  </tr>
490 
491  <tr>
492  <td>power_usart0_enable()</td>
493  <td>Enable the USART 0 module.</td>
494  <td>ATmega640, ATmega1280, ATmega1281, ATmega1284, ATmega128RFA1, ATmega2560, ATmega2561, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega3290PA, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2, ATxmega16A4U, ATxmega32A4U</td>
495  </tr>
496 
497  <tr>
498  <td>power_usart0_disable()</td>
499  <td>Disable the USART 0 module.</td>
500  <td>ATmega640, ATmega1280, ATmega1281, ATmega1284, ATmega128RFA1, ATmega2560, ATmega2561, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega3290PA, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2, ATxmega16A4U, ATxmega32A4U</td>
501  </tr>
502 
503  <tr>
504  <td>power_usart1_enable()</td>
505  <td>Enable the USART 1 module.</td>
506  <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega164P, ATmega324P, ATmega644, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2, ATxmega16A4U, ATxmega32A4U</td>
507  </tr>
508 
509  <tr>
510  <td>power_usart1_disable()</td>
511  <td>Disable the USART 1 module.</td>
512  <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega164P, ATmega324P, ATmega644, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2, ATxmega16A4U, ATxmega32A4U</td>
513  </tr>
514 
515  <tr>
516  <td>power_usart2_enable()</td>
517  <td>Enable the USART 2 module.</td>
518  <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
519  </tr>
520 
521  <tr>
522  <td>power_usart2_disable()</td>
523  <td>Disable the USART 2 module.</td>
524  <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
525  </tr>
526 
527  <tr>
528  <td>power_usart3_enable()</td>
529  <td>Enable the USART 3 module.</td>
530  <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
531  </tr>
532 
533  <tr>
534  <td>power_usart3_disable()</td>
535  <td>Disable the USART 3 module.</td>
536  <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
537  </tr>
538 
539  <tr>
540  <td>power_usartc0_disable()</td>
541  <td> Disable the USART0 module on PortC</td>
542  <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
543  </tr>
544 
545  <tr>
546  <td>power_usartc0_enable()</td>
547  <td> Enable the USART0 module on PortC</td>
548  <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
549  </tr>
550 
551  <tr>
552  <td>power_usartd0_disable()</td>
553  <td> Disable the USART0 module on PortD</td>
554  <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
555  </tr>
556 
557  <tr>
558  <td>power_usartd0_enable()</td>
559  <td> Enable the USART0 module on PortD</td>
560  <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
561  </tr>
562 
563  <tr>
564  <td>power_usarte0_disable()</td>
565  <td> Disable the USART0 module on PortE</td>
566  <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
567  </tr>
568 
569  <tr>
570  <td>power_usarte0_enable()</td>
571  <td> Enable the USART0 module on PortE</td>
572  <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
573  </tr>
574 
575  <tr>
576  <td>power_usartf0_disable()</td>
577  <td> Disable the USART0 module on PortF</td>
578  <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
579  </tr>
580 
581  <tr>
582  <td>power_usartf0_enable()</td>
583  <td> Enable the USART0 module on PortF</td>
584  <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
585  </tr>
586 
587  <tr>
588  <td>power_usb_enable()</td>
589  <td>Enable the USB module.</td>
590  <td>AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATxmega64B1, ATxmega128B1, ATxmega64B3, ATxmega128B3, ATxmega16A4U, ATxmega32A4U, ATxmega128c3, ATxmega256c3, ATxmega16c4, ATxmega32c4</td>
591  </tr>
592 
593  <tr>
594  <td>power_usb_disable()</td>
595  <td>Disable the USB module.</td>
596  <td>AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATxmega64B1, ATxmega128B1, ATxmega64B3, ATxmega128B3, ATxmega16A4U, ATxmega32A4U,ATxmega128c3, ATxmega256c3, ATxmega16c4, ATxmega32c4</td>
597  </tr>
598 
599  <tr>
600  <td>power_usi_enable()</td>
601  <td>Enable the Universal Serial Interface module.</td>
602  <td>ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861</td>
603  </tr>
604 
605  <tr>
606  <td>power_usi_disable()</td>
607  <td>Disable the Universal Serial Interface module.</td>
608  <td>ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861</td>
609  </tr>
610 
611  <tr>
612  <td>power_vadc_enable()</td>
613  <td>Enable the Voltage ADC module.</td>
614  <td>ATmega406</td>
615  </tr>
616 
617  <tr>
618  <td>power_vadc_disable()</td>
619  <td>Disable the Voltage ADC module.</td>
620  <td>ATmega406</td>
621  </tr>
622 
623  <tr>
624  <td>power_all_enable()</td>
625  <td>Enable all modules.</td>
626  <td>ATxmega6A4, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmegaA1, ATxmegaA1U, ATxmega128A3, ATxmega192A3, ATxmega256A3, ATxmegaA3B, ATxmega16D4, ATxmega32D4, ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3, ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega3290PA, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2, ATxmega64B1, ATxmega128B1, ATxmega64B3, ATxmega128B3, ATxmega16A4U, ATxmega32A4U, ATxmega64A3U, ATxmega128A3U, ATxmega192A3U, ATxmega256A3U</td>
627  </tr>
628 
629  <tr>
630  <td>power_all_disable()</td>
631  <td>Disable all modules.</td>
632  <td>ATxmega6A4, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmegaA1, ATxmegaA1U, ATxmega128A3, ATxmega192A3, ATxmega256A3, ATxmegaA3B, ATxmega16D4, ATxmega32D4, ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3, ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega3290PA, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861, ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2, ATxmega64B1, ATxmega128B1, ATxmega64B3, ATxmega128B3, ATxmega16A4U, ATxmega32A4U, ATxmega64A3U, ATxmega128A3U, ATxmega192A3U, ATxmega256A3U</td>
633  </tr>
634 </table>
635 </center>
636 </small>
637 
638 @} */
639 
640 // Xmega A series has AES, EBI and DMA bits
641 // Include any other device on need basis
642 #if defined(__AVR_ATxmega16A4__) \
643 || defined(__AVR_ATxmega16A4U__) \
644 || defined(__AVR_ATxmega32A4U__) \
645 || defined(__AVR_ATxmega32A4__) \
646 || defined(__AVR_ATxmega64A1__) \
647 || defined(__AVR_ATxmega64A1U__) \
648 || defined(__AVR_ATxmega64A3__) \
649 || defined(__AVR_ATxmega64A3U__) \
650 || defined(__AVR_ATxmega64A4U__) \
651 || defined(__AVR_ATxmega128A1__) \
652 || defined(__AVR_ATxmega128A1U__) \
653 || defined(__AVR_ATxmega128A3__) \
654 || defined(__AVR_ATxmega128A3U__) \
655 || defined(__AVR_ATxmega128A4U__) \
656 || defined(__AVR_ATxmega192A3__) \
657 || defined(__AVR_ATxmega192A3U__) \
658 || defined(__AVR_ATxmega256A3__) \
659 || defined(__AVR_ATxmega256A3U__) \
660 || defined(__AVR_ATxmega256A3B__) \
661 || defined(__AVR_ATxmega256A3BU__) \
662 || defined(__AVR_ATxmega384C3__)
663 
664 
665 #define power_aes_enable() (PR_PRGEN &= (uint8_t)~(PR_AES_bm))
666 #define power_aes_disable() (PR_PRGEN |= (uint8_t)PR_AES_bm)
667 
668 #define power_ebi_enable() (PR_PRGEN &= (uint8_t)~(PR_EBI_bm))
669 #define power_ebi_disable() (PR_PRGEN |= (uint8_t)PR_EBI_bm)
670 
671 #define power_dma_enable() (PR_PRGEN &= (uint8_t)~(PR_DMA_bm))
672 #define power_dma_disable() (PR_PRGEN |= (uint8_t)PR_DMA_bm)
673 
674 #define power_daca_enable() (PR_PRPA &= (uint8_t)~(PR_DAC_bm))
675 #define power_daca_disable() (PR_PRPA |= (uint8_t)PR_DAC_bm)
676 #define power_dacb_enable() (PR_PRPB &= (uint8_t)~(PR_DAC_bm))
677 #define power_dacb_disable() (PR_PRPB |= (uint8_t)PR_DAC_bm)
678 
679 #define power_usartc1_enable() (PR_PRPC &= (uint8_t)~(PR_USART1_bm))
680 #define power_usartc1_disable() (PR_PRPC |= (uint8_t)PR_USART1_bm)
681 #define power_usartd1_enable() (PR_PRPD &= (uint8_t)~(PR_USART1_bm))
682 #define power_usartd1_disable() (PR_PRPD |= (uint8_t)PR_USART1_bm)
683 #define power_usarte1_enable() (PR_PRPE &= (uint8_t)~(PR_USART1_bm))
684 #define power_usarte1_disable() (PR_PRPE |= (uint8_t)PR_USART1_bm)
685 #define power_usartf1_enable() (PR_PRPF &= (uint8_t)~(PR_USART1_bm))
686 #define power_usartf1_disable() (PR_PRPF |= (uint8_t)PR_USART1_bm)
687 
688 #if defined(__AVR_ATxmega384C3__) \
689 || defined(__AVR_ATxmega256A3BU__) \
690 || defined(__AVR_ATxmega16A4U__) \
691 || defined(__AVR_ATxmega32A4U__) \
692 || defined(__AVR_ATxmega64A3U__) \
693 || defined(__AVR_ATxmega64A4U__) \
694 || defined(__AVR_ATxmega128A3U__) \
695 || defined(__AVR_ATxmega128A4U__) \
696 || defined(__AVR_ATxmega192A3U__) \
697 || defined(__AVR_ATxmega256A3U__)
698 
699 #define power_usb_enable() (PR_PRGEN &= (uint8_t)~(PR_USB_bm))
700 #define power_usb_disable() (PR_PRGEN &= (uint8_t)(PR_USB_bm))
701 
702 #define power_all_enable() \
703 do { \
704  PR_PRGEN &= (uint8_t)~(PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm|PR_USB_bm); \
705  PR_PRPA &= (uint8_t)~(PR_DAC_bm|PR_ADC_bm|PR_AC_bm); \
706  PR_PRPB &= (uint8_t)~(PR_DAC_bm|PR_ADC_bm|PR_AC_bm); \
707  PR_PRPC &= (uint8_t)~(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
708  PR_PRPD &= (uint8_t)~(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
709  PR_PRPE &= (uint8_t)~(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
710  PR_PRPF &= (uint8_t)~(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
711 } while(0)
712 
713 #define power_all_disable() \
714 do { \
715  PR_PRGEN |= (uint8_t)(PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm|PR_USB_bm); \
716  PR_PRPA |= (uint8_t)(PR_DAC_bm|PR_ADC_bm|PR_AC_bm); \
717  PR_PRPB |= (uint8_t)(PR_DAC_bm|PR_ADC_bm|PR_AC_bm); \
718  PR_PRPC |= (uint8_t)(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
719  PR_PRPD |= (uint8_t)(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
720  PR_PRPE |= (uint8_t)(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
721  PR_PRPF |= (uint8_t)(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
722 } while(0)
723 
724 #else
725 
726 #define power_all_enable() \
727 do { \
728  PR_PRGEN &= (uint8_t)~(PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm); \
729  PR_PRPA &= (uint8_t)~(PR_DAC_bm|PR_ADC_bm|PR_AC_bm); \
730  PR_PRPB &= (uint8_t)~(PR_DAC_bm|PR_ADC_bm|PR_AC_bm); \
731  PR_PRPC &= (uint8_t)~(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
732  PR_PRPD &= (uint8_t)~(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
733  PR_PRPE &= (uint8_t)~(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
734  PR_PRPF &= (uint8_t)~(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
735 } while(0)
736 
737 
738 #define power_all_disable() \
739 do { \
740  PR_PRGEN|= (uint8_t)(PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm); \
741  PR_PRPA |= (uint8_t)(PR_DAC_bm|PR_ADC_bm|PR_AC_bm); \
742  PR_PRPB |= (uint8_t)(PR_DAC_bm|PR_ADC_bm|PR_AC_bm); \
743  PR_PRPC |= (uint8_t)(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
744  PR_PRPD |= (uint8_t)(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
745  PR_PRPE |= (uint8_t)(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
746  PR_PRPF |= (uint8_t)(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
747 } while(0)
748 #endif
749 
750 #endif
751 
752 #if defined(__AVR_ATxmega64D3__) \
753 || defined(__AVR_ATxmega128D3__) \
754 || defined(__AVR_ATxmega192D3__) \
755 || defined(__AVR_ATxmega256D3__)
756 
757 #define power_rtc_enable() (PR_PRGEN &= (uint8_t)~(PR_RTC_bm))
758 #define power_rtc_disable() (PR_PRGEN |= (uint8_t)PR_RTC_bm)
759 
760 #define power_evsys_enable() (PR_PRGEN &= (uint8_t)~(PR_EVSYS_bm))
761 #define power_evsys_disable() (PR_PRGEN |= (uint8_t)PR_EVSYS_bm)
762 
763 #define power_adca_enable() (PR_PRPA &= (uint8_t)~(PR_ADC_bm))
764 #define power_adca_disable() (PR_PRPA |= (uint8_t)PR_ADC_bm)
765 
766 #define power_aca_enable() (PR_PRPA &= (uint8_t)~(PR_AC_bm))
767 #define power_aca_disable() (PR_PRPA |= (uint8_t)PR_AC_bm)
768 
769 #define power_twic_enable() (PR_PRPC &= (uint8_t)~(PR_TWI_bm))
770 #define power_twic_disable() (PR_PRPC |= (uint8_t)PR_TWI_bm)
771 #define power_twie_enable() (PR_PRPE &= (uint8_t)~(PR_TWI_bm))
772 #define power_twie_disable() (PR_PRPE |= (uint8_t)PR_TWI_bm)
773 
774 #define power_usartc0_enable() (PR_PRPC &= (uint8_t)~(PR_USART0_bm))
775 #define power_usartc0_disable() (PR_PRPC |= (uint8_t)PR_USART0_bm)
776 #define power_usartd0_enable() (PR_PRPD &= (uint8_t)~(PR_USART0_bm))
777 #define power_usartd0_disable() (PR_PRPD |= (uint8_t)PR_USART0_bm)
778 #define power_usarte0_enable() (PR_PRPE &= (uint8_t)~(PR_USART0_bm))
779 #define power_usarte0_disable() (PR_PRPE |= (uint8_t)PR_USART0_bm)
780 #define power_usartf0_enable() (PR_PRPF &= (uint8_t)~(PR_USART0_bm))
781 #define power_usartf0_disable() (PR_PRPF |= (uint8_t)PR_USART0_bm)
782 
783 #define power_spic_enable() (PR_PRPC &= (uint8_t)~(PR_SPI_bm))
784 #define power_spic_disable() (PR_PRPC |= (uint8_t)PR_SPI_bm)
785 #define power_spid_enable() (PR_PRPD &= (uint8_t)~(PR_SPI_bm))
786 #define power_spid_disable() (PR_PRPD |= (uint8_t)PR_SPI_bm)
787 
788 #define power_hiresc_enable() (PR_PRPC &= (uint8_t)~(PR_HIRES_bm))
789 #define power_hiresc_disable() (PR_PRPC |= (uint8_t)PR_HIRES_bm)
790 
791 #define power_tc1c_enable() (PR_PRPC &= (uint8_t)~(PR_TC1_bm))
792 #define power_tc1c_disable() (PR_PRPC |= (uint8_t)PR_TC1_bm)
793 
794 #define power_tc0c_enable() (PR_PRPC &= (uint8_t)~(PR_TC0_bm))
795 #define power_tc0c_disable() (PR_PRPC |= (uint8_t)PR_TC0_bm)
796 #define power_tc0d_enable() (PR_PRPD &= (uint8_t)~(PR_TC0_bm))
797 #define power_tc0d_disable() (PR_PRPD |= (uint8_t)PR_TC0_bm)
798 #define power_tc0e_enable() (PR_PRPE &= (uint8_t)~(PR_TC0_bm))
799 #define power_tc0e_disable() (PR_PRPE |= (uint8_t)PR_TC0_bm)
800 #define power_tc0f_enable() (PR_PRPF &= (uint8_t)~(PR_TC0_bm))
801 #define power_tc0f_disable() (PR_PRPF |= (uint8_t)PR_TC0_bm)
802 
803 #define power_all_enable() \
804 do { \
805  PR_PRGEN &= (uint8_t)~(PR_RTC_bm|PR_EVSYS_bm); \
806  PR_PRPA &= (uint8_t)~(PR_ADC_bm|PR_AC_bm); \
807  PR_PRPC &= (uint8_t)~(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
808  PR_PRPD &= (uint8_t)~(PR_USART0_bm|PR_SPI_bm|PR_TC0_bm); \
809  PR_PRPE &= (uint8_t)~(PR_TWI_bm|PR_USART0_bm|PR_TC0_bm); \
810  PR_PRPF &= (uint8_t)~(PR_USART0_bm|PR_TC0_bm); \
811 } while(0)
812 
813 
814 #define power_all_disable() \
815 do { \
816  PR_PRGEN|= (uint8_t)(PR_RTC_bm|PR_EVSYS_bm); \
817  PR_PRPA |= (uint8_t)(PR_ADC_bm|PR_AC_bm); \
818  PR_PRPC |= (uint8_t)(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
819  PR_PRPD |= (uint8_t)(PR_USART0_bm|PR_SPI_bm|PR_TC0_bm); \
820  PR_PRPE |= (uint8_t)(PR_TWI_bm|PR_USART0_bm|PR_TC0_bm); \
821  PR_PRPF |= (uint8_t)(PR_USART0_bm|PR_TC0_bm); \
822 } while(0)
823 #endif
824 
825 #if defined(__AVR_ATxmega16C4__) \
826 || defined(__AVR_ATxmega32C4__) \
827 || defined(__AVR_ATxmega64C3__) \
828 || defined(__AVR_ATxmega128C3__) \
829 || defined(__AVR_ATxmega192C3__) \
830 || defined(__AVR_ATxmega256C3__)
831 
832 #define power_usb_enable() (PR_PRGEN &= (uint8_t)~(PR_USB_bm))
833 #define power_usb_disable() (PR_PRGEN &= (uint8_t)(PR_USB_bm))
834 
835 #define power_aes_enable() (PR_PRGEN &= (uint8_t)~(PR_AES_bm))
836 #define power_aes_disable() (PR_PRGEN |= (uint8_t)PR_AES_bm)
837 
838 #define power_rtc_enable() (PR_PRGEN &= (uint8_t)~(PR_RTC_bm))
839 #define power_rtc_disable() (PR_PRGEN |= (uint8_t)PR_RTC_bm)
840 
841 #define power_evsys_enable() (PR_PRGEN &= (uint8_t)~(PR_EVSYS_bm))
842 #define power_evsys_disable() (PR_PRGEN |= (uint8_t)PR_EVSYS_bm)
843 
844 #define power_dma_enable() (PR_PRGEN &= (uint8_t)~(PR_DMA_bm))
845 #define power_dma_disable() (PR_PRGEN |= (uint8_t)PR_DMA_bm)
846 
847 #define power_adca_enable() (PR_PRPA &= (uint8_t)~(PR_ADC_bm))
848 #define power_adca_disable() (PR_PRPA |= (uint8_t)PR_ADC_bm)
849 
850 #define power_aca_enable() (PR_PRPA &= (uint8_t)~(PR_AC_bm))
851 #define power_aca_disable() (PR_PRPA |= (uint8_t)PR_AC_bm)
852 
853 #define power_twic_enable() (PR_PRPC &= (uint8_t)~(PR_TWI_bm))
854 #define power_twic_disable() (PR_PRPC |= (uint8_t)PR_TWI_bm)
855 #define power_twie_enable() (PR_PRPE &= (uint8_t)~(PR_TWI_bm))
856 #define power_twie_disable() (PR_PRPE |= (uint8_t)PR_TWI_bm)
857 
858 #define power_usartc1_enable() (PR_PRPC &= (uint8_t)~(PR_USART1_bm))
859 #define power_usartc1_disable() (PR_PRPC |= (uint8_t)PR_USART1_bm)
860 
861 #define power_usartc0_enable() (PR_PRPC &= (uint8_t)~(PR_USART0_bm))
862 #define power_usartc0_disable() (PR_PRPC |= (uint8_t)PR_USART0_bm)
863 #define power_usartd0_enable() (PR_PRPD &= (uint8_t)~(PR_USART0_bm))
864 #define power_usartd0_disable() (PR_PRPD |= (uint8_t)PR_USART0_bm)
865 #define power_usarte0_enable() (PR_PRPE &= (uint8_t)~(PR_USART0_bm))
866 #define power_usarte0_disable() (PR_PRPE |= (uint8_t)PR_USART0_bm)
867 #define power_usartf0_enable() (PR_PRPF &= (uint8_t)~(PR_USART0_bm))
868 #define power_usartf0_disable() (PR_PRPF |= (uint8_t)PR_USART0_bm)
869 
870 #define power_spic_enable() (PR_PRPC &= (uint8_t)~(PR_SPI_bm))
871 #define power_spic_disable() (PR_PRPC |= (uint8_t)PR_SPI_bm)
872 #define power_spid_enable() (PR_PRPD &= (uint8_t)~(PR_SPI_bm))
873 #define power_spid_disable() (PR_PRPD |= (uint8_t)PR_SPI_bm)
874 
875 #define power_hiresc_enable() (PR_PRPC &= (uint8_t)~(PR_HIRES_bm))
876 #define power_hiresc_disable() (PR_PRPC |= (uint8_t)PR_HIRES_bm)
877 
878 #define power_tc1c_enable() (PR_PRPC &= (uint8_t)~(PR_TC1_bm))
879 #define power_tc1c_disable() (PR_PRPC |= (uint8_t)PR_TC1_bm)
880 
881 #define power_tc0c_enable() (PR_PRPC &= (uint8_t)~(PR_TC0_bm))
882 #define power_tc0c_disable() (PR_PRPC |= (uint8_t)PR_TC0_bm)
883 #define power_tc0d_enable() (PR_PRPD &= (uint8_t)~(PR_TC0_bm))
884 #define power_tc0d_disable() (PR_PRPD |= (uint8_t)PR_TC0_bm)
885 #define power_tc0e_enable() (PR_PRPE &= (uint8_t)~(PR_TC0_bm))
886 #define power_tc0e_disable() (PR_PRPE |= (uint8_t)PR_TC0_bm)
887 #define power_tc0f_enable() (PR_PRPF &= (uint8_t)~(PR_TC0_bm))
888 #define power_tc0f_disable() (PR_PRPF |= (uint8_t)PR_TC0_bm)
889 
890 #define power_all_enable() \
891 do { \
892  PR_PRGEN &= (uint8_t)~(PR_USB_bm|PR_AES_bm|PR_DMA_bm|PR_RTC_bm|PR_EVSYS_bm); \
893  PR_PRPA &= (uint8_t)~(PR_ADC_bm|PR_AC_bm); \
894  PR_PRPC &= (uint8_t)~(PR_TWI_bm|PR_USART0_bm|PR_USART1_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
895  PR_PRPD &= (uint8_t)~(PR_USART0_bm|PR_SPI_bm|PR_TC0_bm); \
896  PR_PRPE &= (uint8_t)~(PR_TWI_bm|PR_USART0_bm|PR_TC0_bm); \
897  PR_PRPF &= (uint8_t)~(PR_USART0_bm|PR_TC0_bm); \
898  } while(0)
899 
900 #define power_all_disable() \
901 do { \
902  PR_PRGEN |= (uint8_t)(PR_USB_bm|PR_AES_bm|PR_DMA_bm|PR_RTC_bm|PR_EVSYS_bm); \
903  PR_PRPA |= (uint8_t)(PR_ADC_bm|PR_AC_bm); \
904  PR_PRPC |= (uint8_t)(PR_TWI_bm|PR_USART0_bm|PR_USART1_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
905  PR_PRPD |= (uint8_t)(PR_USART0_bm|PR_SPI_bm|PR_TC0_bm); \
906  PR_PRPE |= (uint8_t)(PR_TWI_bm|PR_USART0_bm|PR_TC0_bm); \
907  PR_PRPF |= (uint8_t)(PR_USART0_bm|PR_TC0_bm); \
908  } while(0)
909 
910 #endif
911 
912 #if defined(__AVR_ATxmega16A4__) \
913 || defined(__AVR_ATxmega16A4U__) \
914 || defined(__AVR_ATxmega16D4__) \
915 || defined(__AVR_ATxmega32A4__) \
916 || defined(__AVR_ATxmega32A4U__) \
917 || defined(__AVR_ATxmega32D4__) \
918 || defined(__AVR_ATxmega64A1__) \
919 || defined(__AVR_ATxmega64A1U__) \
920 || defined(__AVR_ATxmega64A3__) \
921 || defined(__AVR_ATxmega64A3U__) \
922 || defined(__AVR_ATxmega64A4U__) \
923 || defined(__AVR_ATxmega128A1__) \
924 || defined(__AVR_ATxmega128A1U__) \
925 || defined(__AVR_ATxmega128A3__) \
926 || defined(__AVR_ATxmega128A3U__) \
927 || defined(__AVR_ATxmega128A4U__) \
928 || defined(__AVR_ATxmega192A3__) \
929 || defined(__AVR_ATxmega192A3U__) \
930 || defined(__AVR_ATxmega256A3__) \
931 || defined(__AVR_ATxmega256A3U__) \
932 || defined(__AVR_ATxmega256A3B__) \
933 || defined(__AVR_ATxmega256A3BU__) \
934 || defined(__AVR_ATxmega384C3__)
935 
936 
937 #define power_rtc_enable() (PR_PRGEN &= (uint8_t)~(PR_RTC_bm))
938 #define power_rtc_disable() (PR_PRGEN |= (uint8_t)PR_RTC_bm)
939 
940 #define power_evsys_enable() (PR_PRGEN &= (uint8_t)~(PR_EVSYS_bm))
941 #define power_evsys_disable() (PR_PRGEN |= (uint8_t)PR_EVSYS_bm)
942 
943 #define power_adca_enable() (PR_PRPA &= (uint8_t)~(PR_ADC_bm))
944 #define power_adca_disable() (PR_PRPA |= (uint8_t)PR_ADC_bm)
945 #define power_adcb_enable() (PR_PRPB &= (uint8_t)~(PR_ADC_bm))
946 #define power_adcb_disable() (PR_PRPB |= (uint8_t)PR_ADC_bm)
947 
948 #define power_aca_enable() (PR_PRPA &= (uint8_t)~(PR_AC_bm))
949 #define power_aca_disable() (PR_PRPA |= (uint8_t)PR_AC_bm)
950 #define power_acb_enable() (PR_PRPB &= (uint8_t)~(PR_AC_bm))
951 #define power_acb_disable() (PR_PRPB |= (uint8_t)PR_AC_bm)
952 
953 #define power_twic_enable() (PR_PRPC &= (uint8_t)~(PR_TWI_bm))
954 #define power_twic_disable() (PR_PRPC |= (uint8_t)PR_TWI_bm)
955 #define power_twid_enable() (PR_PRPD &= (uint8_t)~(PR_TWI_bm))
956 #define power_twid_disable() (PR_PRPD |= (uint8_t)PR_TWI_bm)
957 #define power_twie_enable() (PR_PRPE &= (uint8_t)~(PR_TWI_bm))
958 #define power_twie_disable() (PR_PRPE |= (uint8_t)PR_TWI_bm)
959 #define power_twif_enable() (PR_PRPF &= (uint8_t)~(PR_TWI_bm))
960 #define power_twif_disable() (PR_PRPF |= (uint8_t)PR_TWI_bm)
961 
962 #define power_usartc0_enable() (PR_PRPC &= (uint8_t)~(PR_USART0_bm))
963 #define power_usartc0_disable() (PR_PRPC |= (uint8_t)PR_USART0_bm)
964 #define power_usartd0_enable() (PR_PRPD &= (uint8_t)~(PR_USART0_bm))
965 #define power_usartd0_disable() (PR_PRPD |= (uint8_t)PR_USART0_bm)
966 #define power_usarte0_enable() (PR_PRPE &= (uint8_t)~(PR_USART0_bm))
967 #define power_usarte0_disable() (PR_PRPE |= (uint8_t)PR_USART0_bm)
968 #define power_usartf0_enable() (PR_PRPF &= (uint8_t)~(PR_USART0_bm))
969 #define power_usartf0_disable() (PR_PRPF |= (uint8_t)PR_USART0_bm)
970 
971 #define power_spic_enable() (PR_PRPC &= (uint8_t)~(PR_SPI_bm))
972 #define power_spic_disable() (PR_PRPC |= (uint8_t)PR_SPI_bm)
973 #define power_spid_enable() (PR_PRPD &= (uint8_t)~(PR_SPI_bm))
974 #define power_spid_disable() (PR_PRPD |= (uint8_t)PR_SPI_bm)
975 #define power_spie_enable() (PR_PRPE &= (uint8_t)~(PR_SPI_bm))
976 #define power_spie_disable() (PR_PRPE |= (uint8_t)PR_SPI_bm)
977 #define power_spif_enable() (PR_PRPF &= (uint8_t)~(PR_SPI_bm))
978 #define power_spif_disable() (PR_PRPF |= (uint8_t)PR_SPI_bm)
979 
980 #define power_hiresc_enable() (PR_PRPC &= (uint8_t)~(PR_HIRES_bm))
981 #define power_hiresc_disable() (PR_PRPC |= (uint8_t)PR_HIRES_bm)
982 #define power_hiresd_enable() (PR_PRPD &= (uint8_t)~(PR_HIRES_bm))
983 #define power_hiresd_disable() (PR_PRPD |= (uint8_t)PR_HIRES_bm)
984 #define power_hirese_enable() (PR_PRPE &= (uint8_t)~(PR_HIRES_bm))
985 #define power_hirese_disable() (PR_PRPE |= (uint8_t)PR_HIRES_bm)
986 #define power_hiresf_enable() (PR_PRPF &= (uint8_t)~(PR_HIRES_bm))
987 #define power_hiresf_disable() (PR_PRPF |= (uint8_t)PR_HIRES_bm)
988 
989 #define power_tc1c_enable() (PR_PRPC &= (uint8_t)~(PR_TC1_bm))
990 #define power_tc1c_disable() (PR_PRPC |= (uint8_t)PR_TC1_bm)
991 #define power_tc1d_enable() (PR_PRPD &= (uint8_t)~(PR_TC1_bm))
992 #define power_tc1d_disable() (PR_PRPD |= (uint8_t)PR_TC1_bm)
993 #define power_tc1e_enable() (PR_PRPE &= (uint8_t)~(PR_TC1_bm))
994 #define power_tc1e_disable() (PR_PRPE |= (uint8_t)PR_TC1_bm)
995 #define power_tc1f_enable() (PR_PRPF &= (uint8_t)~(PR_TC1_bm))
996 #define power_tc1f_disable() (PR_PRPF |= (uint8_t)PR_TC1_bm)
997 
998 #define power_tc0c_enable() (PR_PRPC &= (uint8_t)~(PR_TC0_bm))
999 #define power_tc0c_disable() (PR_PRPC |= (uint8_t)PR_TC0_bm)
1000 #define power_tc0d_enable() (PR_PRPD &= (uint8_t)~(PR_TC0_bm))
1001 #define power_tc0d_disable() (PR_PRPD |= (uint8_t)PR_TC0_bm)
1002 #define power_tc0e_enable() (PR_PRPE &= (uint8_t)~(PR_TC0_bm))
1003 #define power_tc0e_disable() (PR_PRPE |= (uint8_t)PR_TC0_bm)
1004 #define power_tc0f_enable() (PR_PRPF &= (uint8_t)~(PR_TC0_bm))
1005 #define power_tc0f_disable() (PR_PRPF |= (uint8_t)PR_TC0_bm)
1006 
1007 #endif
1008 
1009 #if defined(__AVR_ATxmega64D4__) \
1010 || defined(__AVR_ATxmega128D4__)
1011 
1012 #define power_rtc_enable() (PR_PRGEN &= (uint8_t)~(PR_RTC_bm))
1013 #define power_rtc_disable() (PR_PRGEN |= (uint8_t)PR_RTC_bm)
1014 
1015 #define power_evsys_enable() (PR_PRGEN &= (uint8_t)~(PR_EVSYS_bm))
1016 #define power_evsys_disable() (PR_PRGEN |= (uint8_t)PR_EVSYS_bm)
1017 
1018 #define power_adca_enable() (PR_PRPA &= (uint8_t)~(PR_ADC_bm))
1019 #define power_adca_disable() (PR_PRPA |= (uint8_t)PR_ADC_bm)
1020 
1021 #define power_aca_enable() (PR_PRPA &= (uint8_t)~(PR_AC_bm))
1022 #define power_aca_disable() (PR_PRPA |= (uint8_t)PR_AC_bm)
1023 
1024 #define power_twic_enable() (PR_PRPC &= (uint8_t)~(PR_TWI_bm))
1025 #define power_twic_disable() (PR_PRPC |= (uint8_t)PR_TWI_bm)
1026 #define power_twie_enable() (PR_PRPE &= (uint8_t)~(PR_TWI_bm))
1027 #define power_twie_disable() (PR_PRPE |= (uint8_t)PR_TWI_bm)
1028 
1029 #define power_usartc0_enable() (PR_PRPC &= (uint8_t)~(PR_USART0_bm))
1030 #define power_usartc0_disable() (PR_PRPC |= (uint8_t)PR_USART0_bm)
1031 #define power_usartd0_enable() (PR_PRPD &= (uint8_t)~(PR_USART0_bm))
1032 #define power_usartd0_disable() (PR_PRPD |= (uint8_t)PR_USART0_bm)
1033 #define power_usarte0_enable() (PR_PRPE &= (uint8_t)~(PR_USART0_bm))
1034 #define power_usarte0_disable() (PR_PRPE |= (uint8_t)PR_USART0_bm)
1035 #define power_usartf0_enable() (PR_PRPF &= (uint8_t)~(PR_USART0_bm))
1036 #define power_usartf0_disable() (PR_PRPF |= (uint8_t)PR_USART0_bm)
1037 
1038 #define power_spic_enable() (PR_PRPC &= (uint8_t)~(PR_SPI_bm))
1039 #define power_spic_disable() (PR_PRPC |= (uint8_t)PR_SPI_bm)
1040 #define power_spid_enable() (PR_PRPD &= (uint8_t)~(PR_SPI_bm))
1041 #define power_spid_disable() (PR_PRPD |= (uint8_t)PR_SPI_bm)
1042 
1043 #define power_hiresc_enable() (PR_PRPC &= (uint8_t)~(PR_HIRES_bm))
1044 #define power_hiresc_disable() (PR_PRPC |= (uint8_t)PR_HIRES_bm)
1045 
1046 #define power_tc1c_enable() (PR_PRPC &= (uint8_t)~(PR_TC1_bm))
1047 #define power_tc1c_disable() (PR_PRPC |= (uint8_t)PR_TC1_bm)
1048 
1049 #define power_tc0c_enable() (PR_PRPC &= (uint8_t)~(PR_TC0_bm))
1050 #define power_tc0c_disable() (PR_PRPC |= (uint8_t)PR_TC0_bm)
1051 #define power_tc0d_enable() (PR_PRPD &= (uint8_t)~(PR_TC0_bm))
1052 #define power_tc0d_disable() (PR_PRPD |= (uint8_t)PR_TC0_bm)
1053 #define power_tc0e_enable() (PR_PRPE &= (uint8_t)~(PR_TC0_bm))
1054 #define power_tc0e_disable() (PR_PRPE |= (uint8_t)PR_TC0_bm)
1055 #define power_tc0f_enable() (PR_PRPF &= (uint8_t)~(PR_TC0_bm))
1056 #define power_tc0f_disable() (PR_PRPF |= (uint8_t)PR_TC0_bm)
1057 
1058 #define power_all_enable() \
1059 do { \
1060  PR_PRGEN &= (uint8_t)~(PR_RTC_bm|PR_EVSYS_bm); \
1061  PR_PRPA &= (uint8_t)~(PR_ADC_bm|PR_AC_bm); \
1062  PR_PRPC &= (uint8_t)~(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
1063  PR_PRPD &= (uint8_t)~(PR_USART0_bm|PR_SPI_bm|PR_TC0_bm); \
1064  PR_PRPE &= (uint8_t)~(PR_TWI_bm|PR_USART0_bm|PR_TC0_bm); \
1065  PR_PRPF &= (uint8_t)~(PR_USART0_bm|PR_TC0_bm); \
1066  } while(0)
1067 
1068 #define power_all_disable() \
1069 do { \
1070  PR_PRGEN |= (uint8_t)(PR_RTC_bm|PR_EVSYS_bm); \
1071  PR_PRPA |= (uint8_t)(PR_ADC_bm|PR_AC_bm); \
1072  PR_PRPC |= (uint8_t)(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
1073  PR_PRPD |= (uint8_t)(PR_USART0_bm|PR_SPI_bm|PR_TC0_bm); \
1074  PR_PRPE |= (uint8_t)(PR_TWI_bm|PR_USART0_bm|PR_TC0_bm); \
1075  PR_PRPF |= (uint8_t)(PR_USART0_bm|PR_TC0_bm); \
1076  } while(0)
1077 
1078 #endif
1079 
1080 #if defined(__AVR_ATxmega16D4__) \
1081 || defined(__AVR_ATxmega32D4__)
1082 
1083 #define power_all_enable() \
1084 do { \
1085  PR_PRGEN &= (uint8_t)~(PR_RTC_bm|PR_EVSYS_bm); \
1086  PR_PRPA &= (uint8_t)~(PR_ADC_bm|PR_AC_bm); \
1087  PR_PRPB &= (uint8_t)~(PR_ADC_bm|PR_AC_bm); \
1088  PR_PRPC &= (uint8_t)~(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
1089  PR_PRPD &= (uint8_t)~(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
1090  PR_PRPE &= (uint8_t)~(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
1091  PR_PRPF &= (uint8_t)~(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
1092 } while(0)
1093 
1094 
1095 #define power_all_disable() \
1096 do { \
1097  PR_PRGEN|= (uint8_t)(PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm); \
1098  PR_PRPA |= (uint8_t)(PR_ADC_bm|PR_AC_bm); \
1099  PR_PRPB |= (uint8_t)(PR_ADC_bm|PR_AC_bm); \
1100  PR_PRPC |= (uint8_t)(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
1101  PR_PRPD |= (uint8_t)(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
1102  PR_PRPE |= (uint8_t)(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
1103  PR_PRPF |= (uint8_t)(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
1104 } while(0)
1105 
1106 #elif defined (__AVR_ATxmega64B1__) \
1107 || defined (__AVR_ATxmega64B3__) \
1108 || defined (__AVR_ATxmega128B1__) \
1109 || defined (__AVR_ATxmega128B3__)
1110 #define power_lcd_enable() (PR_PRGEN &= (uint8_t)~(PR_LCD_bm))
1111 #define power_lcd_disable() (PR_PRGEN |= (uint8_t)PR_LCD_bm)
1112 
1113 #define power_usb_enable() (PR_PRGEN &= (uint8_t)~(PR_USB_bm))
1114 #define power_usb_disable() (PR_PRGEN |= (uint8_t)PR_USB_bm)
1115 
1116 #define power_aes_enable() (PR_PRGEN &= (uint8_t)~(PR_AES_bm))
1117 #define power_aes_disable() (PR_PRGEN |= (uint8_t)PR_AES_bm)
1118 
1119 #define power_rtc_enable() (PR_PRGEN &= (uint8_t)~(PR_RTC_bm))
1120 #define power_rtc_disable() (PR_PRGEN |= (uint8_t)PR_RTC_bm)
1121 
1122 #define power_evsys_enable() (PR_PRGEN &= (uint8_t)~(PR_EVSYS_bm))
1123 #define power_evsys_disable() (PR_PRGEN |= (uint8_t)PR_EVSYS_bm)
1124 
1125 #define power_dma_enable() (PR_PRGEN &= (uint8_t)~(PR_DMA_bm))
1126 #define power_dma_disable() (PR_PRGEN |= (uint8_t)PR_DMA_bm)
1127 
1128 #define power_adca_enable() (PR_PRPA &= (uint8_t)~(PR_ADC_bm))
1129 #define power_adca_disable() (PR_PRPA |= (uint8_t)PR_ADC_bm)
1130 #define power_adcb_enable() (PR_PRPB &= (uint8_t)~(PR_ADC_bm))
1131 #define power_adcb_disable() (PR_PRPB |= (uint8_t)PR_ADC_bm)
1132 
1133 #define power_aca_enable() (PR_PRPA &= (uint8_t)~(PR_AC_bm))
1134 #define power_aca_disable() (PR_PRPA |= (uint8_t)PR_AC_bm)
1135 #define power_acb_enable() (PR_PRPB &= (uint8_t)~(PR_AC_bm))
1136 #define power_acb_disable() (PR_PRPB |= (uint8_t)PR_AC_bm)
1137 
1138 #define power_twic_enable() (PR_PRPC &= (uint8_t)~(PR_TWI_bm))
1139 #define power_twic_disable() (PR_PRPC |= (uint8_t)PR_TWI_bm)
1140 
1141 #define power_usartc0_enable() (PR_PRPC &= (uint8_t)~(PR_USART0_bm))
1142 #define power_usartc0_disable() (PR_PRPC |= (uint8_t)PR_USART0_bm)
1143 #define power_usarte0_enable() (PR_PRPE &= (uint8_t)~(PR_USART0_bm))
1144 #define power_usarte0_disable() (PR_PRPE |= (uint8_t)PR_USART0_bm)
1145 
1146 #define power_spic_enable() (PR_PRPC &= (uint8_t)~(PR_SPI_bm))
1147 #define power_spic_disable() (PR_PRPC |= (uint8_t)PR_SPI_bm)
1148 
1149 #define power_hiresc_enable() (PR_PRPC &= (uint8_t)~(PR_HIRES_bm))
1150 #define power_hiresc_disable() (PR_PRPC |= (uint8_t)PR_HIRES_bm)
1151 
1152 #define power_tc1c_enable() (PR_PRPC &= (uint8_t)~(PR_TC1_bm))
1153 #define power_tc1c_disable() (PR_PRPC |= (uint8_t)PR_TC1_bm)
1154 
1155 #define power_tc0c_enable() (PR_PRPC &= (uint8_t)~(PR_TC0_bm))
1156 #define power_tc0c_disable() (PR_PRPC |= (uint8_t)PR_TC0_bm)
1157 #define power_tc0e_enable() (PR_PRPE &= (uint8_t)~(PR_TC0_bm))
1158 #define power_tc0e_disable() (PR_PRPE |= (uint8_t)PR_TC0_bm)
1159 
1160 #define power_all_enable() \
1161 do { \
1162  PR_PRGEN &= (uint8_t)~(PR_LCD_bm|PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm); \
1163  PR_PRPA &= (uint8_t)~(PR_ADC_bm|PR_AC_bm); \
1164  PR_PRPB &= (uint8_t)~(PR_ADC_bm|PR_AC_bm); \
1165  PR_PRPC &= (uint8_t)~(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
1166  PR_PRPE &= (uint8_t)~(PR_USART0_bm|PR_TC0_bm); \
1167  } while(0)
1168 
1169 #define power_all_disable() \
1170 do { \
1171  PR_PRGEN |= (uint8_t)(PR_LCD_bm|PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm); \
1172  PR_PRPA |= (uint8_t)(PR_ADC_bm|PR_AC_bm); \
1173  PR_PRPB |= (uint8_t)(PR_ADC_bm|PR_AC_bm); \
1174  PR_PRPC |= (uint8_t)(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
1175  PR_PRPE |= (uint8_t)(PR_USART0_bm|PR_TC0_bm); \
1176  } while(0)
1177 
1178 #elif defined(__AVR_ATmega640__) \
1179 || defined(__AVR_ATmega1280__) \
1180 || defined(__AVR_ATmega1281__) \
1181 || defined(__AVR_ATmega2560__) \
1182 || defined(__AVR_ATmega2561__)
1183 
1184 #define power_adc_enable() (PRR0 &= (uint8_t)~(1 << PRADC))
1185 #define power_adc_disable() (PRR0 |= (uint8_t)(1 << PRADC))
1186 
1187 #define power_spi_enable() (PRR0 &= (uint8_t)~(1 << PRSPI))
1188 #define power_spi_disable() (PRR0 |= (uint8_t)(1 << PRSPI))
1189 
1190 #define power_twi_enable() (PRR0 &= (uint8_t)~(1 << PRTWI))
1191 #define power_twi_disable() (PRR0 |= (uint8_t)(1 << PRTWI))
1192 
1193 #define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRTIM0))
1194 #define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRTIM0))
1195 
1196 #define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRTIM1))
1197 #define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRTIM1))
1198 
1199 #define power_timer2_enable() (PRR0 &= (uint8_t)~(1 << PRTIM2))
1200 #define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRTIM2))
1201 
1202 #define power_timer3_enable() (PRR1 &= (uint8_t)~(1 << PRTIM3))
1203 #define power_timer3_disable() (PRR1 |= (uint8_t)(1 << PRTIM3))
1204 
1205 #define power_timer4_enable() (PRR1 &= (uint8_t)~(1 << PRTIM4))
1206 #define power_timer4_disable() (PRR1 |= (uint8_t)(1 << PRTIM4))
1207 
1208 #define power_timer5_enable() (PRR1 &= (uint8_t)~(1 << PRTIM5))
1209 #define power_timer5_disable() (PRR1 |= (uint8_t)(1 << PRTIM5))
1210 
1211 #define power_usart0_enable() (PRR0 &= (uint8_t)~(1 << PRUSART0))
1212 #define power_usart0_disable() (PRR0 |= (uint8_t)(1 << PRUSART0))
1213 
1214 #define power_usart1_enable() (PRR1 &= (uint8_t)~(1 << PRUSART1))
1215 #define power_usart1_disable() (PRR1 |= (uint8_t)(1 << PRUSART1))
1216 
1217 #define power_usart2_enable() (PRR1 &= (uint8_t)~(1 << PRUSART2))
1218 #define power_usart2_disable() (PRR1 |= (uint8_t)(1 << PRUSART2))
1219 
1220 #define power_usart3_enable() (PRR1 &= (uint8_t)~(1 << PRUSART3))
1221 #define power_usart3_disable() (PRR1 |= (uint8_t)(1 << PRUSART3))
1222 
1223 #define power_all_enable() \
1224 do{ \
1225  PRR0 &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRUSART0)); \
1226  PRR1 &= (uint8_t)~((1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTIM5)|(1<<PRUSART1)|(1<<PRUSART2)|(1<<PRUSART3)); \
1227 }while(0)
1228 
1229 #define power_all_disable() \
1230 do{ \
1231  PRR0 |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRUSART0)); \
1232  PRR1 |= (uint8_t)((1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTIM5)|(1<<PRUSART1)|(1<<PRUSART2)|(1<<PRUSART3)); \
1233 }while(0)
1234 
1235 
1236 #elif defined(__AVR_ATmega128RFA1__)
1237 
1238 #define power_adc_enable() (PRR0 &= (uint8_t)~(1 << PRADC))
1239 #define power_adc_disable() (PRR0 |= (uint8_t)(1 << PRADC))
1240 
1241 #define power_spi_enable() (PRR0 &= (uint8_t)~(1 << PRSPI))
1242 #define power_spi_disable() (PRR0 |= (uint8_t)(1 << PRSPI))
1243 
1244 #define power_twi_enable() (PRR0 &= (uint8_t)~(1 << PRTWI))
1245 #define power_twi_disable() (PRR0 |= (uint8_t)(1 << PRTWI))
1246 
1247 #define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRTIM0))
1248 #define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRTIM0))
1249 
1250 #define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRTIM1))
1251 #define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRTIM1))
1252 
1253 #define power_timer2_enable() (PRR0 &= (uint8_t)~(1 << PRTIM2))
1254 #define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRTIM2))
1255 
1256 #define power_timer3_enable() (PRR1 &= (uint8_t)~(1 << PRTIM3))
1257 #define power_timer3_disable() (PRR1 |= (uint8_t)(1 << PRTIM3))
1258 
1259 #define power_timer4_enable() (PRR1 &= (uint8_t)~(1 << PRTIM4))
1260 #define power_timer4_disable() (PRR1 |= (uint8_t)(1 << PRTIM4))
1261 
1262 #define power_timer5_enable() (PRR1 &= (uint8_t)~(1 << PRTIM5))
1263 #define power_timer5_disable() (PRR1 |= (uint8_t)(1 << PRTIM5))
1264 
1265 #define power_usart0_enable() (PRR0 &= (uint8_t)~(1 << PRUSART0))
1266 #define power_usart0_disable() (PRR0 |= (uint8_t)(1 << PRUSART0))
1267 
1268 #define power_usart1_enable() (PRR1 &= (uint8_t)~(1 << PRUSART1))
1269 #define power_usart1_disable() (PRR1 |= (uint8_t)(1 << PRUSART1))
1270 
1271 #define power_all_enable() \
1272 do{ \
1273  PRR0 &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRUSART0)); \
1274  PRR1 &= (uint8_t)~((1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTIM5)|(1<<PRUSART1)); \
1275 }while(0)
1276 
1277 #define power_all_disable() \
1278 do{ \
1279  PRR0 |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRUSART0)); \
1280  PRR1 |= (uint8_t)((1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTIM5)|(1<<PRUSART1)); \
1281 }while(0)
1282 
1283 #elif defined(__AVR_ATmega256RFR2__) \
1284 || defined(__AVR_ATmega128RFR2__) \
1285 || defined(__AVR_ATmega64RFR2__) \
1286 || defined(__AVR_ATmega2564RFR2__) \
1287 || defined(__AVR_ATmega1284RFR2__) \
1288 || defined(__AVR_ATmega644RFR2__) \
1289 
1290 #define power_adc_enable() (PRR0 &= (uint8_t)~(1 << PRADC))
1291 #define power_adc_disable() (PRR0 |= (uint8_t)(1 << PRADC))
1292 
1293 #define power_usart0_enable() (PRR0 &= (uint8_t)~(1 << PRUSART0))
1294 #define power_usart0_disable() (PRR0 |= (uint8_t)(1 << PRUSART0))
1295 
1296 #define power_spi_enable() (PRR0 &= (uint8_t)~(1 << PRSPI))
1297 #define power_spi_disable() (PRR0 |= (uint8_t)(1 << PRSPI))
1298 
1299 #define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRTIM1))
1300 #define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRTIM1))
1301 
1302 #define power_pga_enable() (PRR0 &= (uint8_t)~(1 << PRPGA))
1303 #define power_pga_disable() (PRR0 |= (uint8_t)(1 << PRPGA))
1304 
1305 #define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRTIM0))
1306 #define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRTIM0))
1307 
1308 #define power_timer2_enable() (PRR0 &= (uint8_t)~(1 << PRTIM2))
1309 #define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRTIM2))
1310 
1311 #define power_twi_enable() (PRR0 &= (uint8_t)~(1 << PRTWI))
1312 #define power_twi_disable() (PRR0 |= (uint8_t)(1 << PRTWI))
1313 
1314 #define power_usart1_enable() (PRR1 &= (uint8_t)~(1 << PRUSART1))
1315 #define power_usart1_disable() (PRR1 |= (uint8_t)(1 << PRUSART1))
1316 
1317 #define power_timer3_enable() (PRR1 &= (uint8_t)~(1 << PRTIM3))
1318 #define power_timer3_disable() (PRR1 |= (uint8_t)(1 << PRTIM3))
1319 
1320 #define power_timer4_enable() (PRR1 &= (uint8_t)~(1 << PRTIM4))
1321 #define power_timer4_disable() (PRR1 |= (uint8_t)(1 << PRTIM4))
1322 
1323 #define power_timer5_enable() (PRR1 &= (uint8_t)~(1 << PRTIM5))
1324 #define power_timer5_disable() (PRR1 |= (uint8_t)(1 << PRTIM5))
1325 
1326 #define power_transceiver_enable() (PRR1 &= (uint8_t)~(1 << PRTRX24))
1327 #define power_transceiver_disable() (PRR1 |= (uint8_t)(1 << PRTRX24))
1328 
1329 #define power_ram0_enable() (PRR2 &= (uint8_t)~(1 << PRRAM0))
1330 #define power_ram0_disable() (PRR2 |= (uint8_t)(1 << PRRAM0))
1331 
1332 #define power_ram1_enable() (PRR2 &= (uint8_t)~(1 << PRRAM1))
1333 #define power_ram1_disable() (PRR2 |= (uint8_t)(1 << PRRAM1))
1334 
1335 #define power_ram2_enable() (PRR2 &= (uint8_t)~(1 << PRRAM2))
1336 #define power_ram2_disable() (PRR2 |= (uint8_t)(1 << PRRAM2))
1337 
1338 #define power_ram3_enable() (PRR2 &= (uint8_t)~(1 << PRRAM3))
1339 #define power_ram3_disable() (PRR2 |= (uint8_t)(1 << PRRAM3))
1340 
1341 #define power_all_enable() \
1342 do{ \
1343  PRR0 &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRUSART0)); \
1344  PRR1 &= (uint8_t)~((1<<PRUSART1)|(1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTRX24)); \
1345  PRR2 &= (uint8_t)~((1<<PRRAM0)|(1<<PRRAM1)|(1<<PRRAM2)|(1<<PRRAM3)); \
1346 }while(0)
1347 
1348 #define power_all_disable() \
1349 do{ \
1350  PRR0 |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRUSART0)); \
1351  PRR1 |= (uint8_t)((1<<PRUSART1)|(1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTRX24)); \
1352  PRR2 |= (uint8_t)((1<<PRRAM0)|(1<<PRRAM1)|(1<<PRRAM2)|(1<<PRRAM3)); \
1353 }while(0)
1354 
1355 #elif defined(__AVR_AT90USB646__) \
1356 || defined(__AVR_AT90USB647__) \
1357 || defined(__AVR_AT90USB1286__) \
1358 || defined(__AVR_AT90USB1287__)
1359 
1360 #define power_adc_enable() (PRR0 &= (uint8_t)~(1 << PRADC))
1361 #define power_adc_disable() (PRR0 |= (uint8_t)(1 << PRADC))
1362 
1363 #define power_spi_enable() (PRR0 &= (uint8_t)~(1 << PRSPI))
1364 #define power_spi_disable() (PRR0 |= (uint8_t)(1 << PRSPI))
1365 
1366 #define power_twi_enable() (PRR0 &= (uint8_t)~(1 << PRTWI))
1367 #define power_twi_disable() (PRR0 |= (uint8_t)(1 << PRTWI))
1368 
1369 #define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRTIM0))
1370 #define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRTIM0))
1371 
1372 #define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRTIM1))
1373 #define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRTIM1))
1374 
1375 #define power_timer2_enable() (PRR0 &= (uint8_t)~(1 << PRTIM2))
1376 #define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRTIM2))
1377 
1378 #define power_timer3_enable() (PRR1 &= (uint8_t)~(1 << PRTIM3))
1379 #define power_timer3_disable() (PRR1 |= (uint8_t)(1 << PRTIM3))
1380 
1381 #define power_usart1_enable() (PRR1 &= (uint8_t)~(1 << PRUSART1))
1382 #define power_usart1_disable() (PRR1 |= (uint8_t)(1 << PRUSART1))
1383 
1384 #define power_usb_enable() (PRR1 &= (uint8_t)~(1 << PRUSB))
1385 #define power_usb_disable() (PRR1 |= (uint8_t)(1 << PRUSB))
1386 
1387 #define power_all_enable() \
1388 do{ \
1389  PRR0 &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)); \
1390  PRR1 &= (uint8_t)~((1<<PRTIM3)|(1<<PRUSART1)|(1<<PRUSB)); \
1391 }while(0)
1392 
1393 #define power_all_disable() \
1394 do{ \
1395  PRR0 |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)); \
1396  PRR1 |= (uint8_t)((1<<PRTIM3)|(1<<PRUSART1)|(1<<PRUSB)); \
1397 }while(0)
1398 
1399 
1400 #elif defined(__AVR_ATmega32U4__) \
1401 || defined(__AVR_ATmega16U4__)
1402 
1403 
1404 #define power_adc_enable() (PRR0 &= (uint8_t)~(1 << PRADC))
1405 #define power_adc_disable() (PRR0 |= (uint8_t)(1 << PRADC))
1406 
1407 #define power_usart0_enable() (PRR0 &= (uint8_t)~(1 << PRUSART0))
1408 #define power_usart0_disable() (PRR0 |= (uint8_t)(1 << PRUSART0))
1409 
1410 #define power_spi_enable() (PRR0 &= (uint8_t)~(1 << PRSPI))
1411 #define power_spi_disable() (PRR0 |= (uint8_t)(1 << PRSPI))
1412 
1413 #define power_twi_enable() (PRR0 &= (uint8_t)~(1 << PRTWI))
1414 #define power_twi_disable() (PRR0 |= (uint8_t)(1 << PRTWI))
1415 
1416 #define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRTIM0))
1417 #define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRTIM0))
1418 
1419 #define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRTIM1))
1420 #define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRTIM1))
1421 
1422 #define power_timer2_enable() (PRR0 &= (uint8_t)~(1 << PRTIM2))
1423 #define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRTIM2))
1424 
1425 #define power_timer3_enable() (PRR1 &= (uint8_t)~(1 << PRTIM3))
1426 #define power_timer3_disable() (PRR1 |= (uint8_t)(1 << PRTIM3))
1427 
1428 #define power_usart1_enable() (PRR1 &= (uint8_t)~(1 << PRUSART1))
1429 #define power_usart1_disable() (PRR1 |= (uint8_t)(1 << PRUSART1))
1430 
1431 #define power_usb_enable() (PRR1 &= (uint8_t)~(1 << PRUSB))
1432 #define power_usb_disable() (PRR1 |= (uint8_t)(1 << PRUSB))
1433 
1434 #define power_all_enable() \
1435 do{ \
1436  PRR0 &= (uint8_t)~((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)); \
1437  PRR1 &= (uint8_t)~((1<<PRTIM3)|(1<<PRUSART1)|(1<<PRUSB)); \
1438 }while(0)
1439 
1440 #define power_all_disable() \
1441 do{ \
1442  PRR0 |= (uint8_t)((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)); \
1443  PRR1 |= (uint8_t)((1<<PRTIM3)|(1<<PRUSART1)|(1<<PRUSB)); \
1444 }while(0)
1445 
1446 
1447 #elif defined(__AVR_ATmega32U6__)
1448 
1449 
1450 #define power_adc_enable() (PRR0 &= (uint8_t)~(1 << PRADC))
1451 #define power_adc_disable() (PRR0 |= (uint8_t)(1 << PRADC))
1452 
1453 #define power_spi_enable() (PRR0 &= (uint8_t)~(1 << PRSPI))
1454 #define power_spi_disable() (PRR0 |= (uint8_t)(1 << PRSPI))
1455 
1456 #define power_twi_enable() (PRR0 &= (uint8_t)~(1 << PRTWI))
1457 #define power_twi_disable() (PRR0 |= (uint8_t)(1 << PRTWI))
1458 
1459 #define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRTIM0))
1460 #define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRTIM0))
1461 
1462 #define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRTIM1))
1463 #define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRTIM1))
1464 
1465 #define power_timer2_enable() (PRR0 &= (uint8_t)~(1 << PRTIM2))
1466 #define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRTIM2))
1467 
1468 #define power_timer3_enable() (PRR1 &= (uint8_t)~(1 << PRTIM3))
1469 #define power_timer3_disable() (PRR1 |= (uint8_t)(1 << PRTIM3))
1470 
1471 #define power_usart1_enable() (PRR1 &= (uint8_t)~(1 << PRUSART1))
1472 #define power_usart1_disable() (PRR1 |= (uint8_t)(1 << PRUSART1))
1473 
1474 #define power_usb_enable() (PRR1 &= (uint8_t)~(1 << PRUSB))
1475 #define power_usb_disable() (PRR1 |= (uint8_t)(1 << PRUSB))
1476 
1477 #define power_all_enable() \
1478 do{ \
1479  PRR0 &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)); \
1480  PRR1 &= (uint8_t)~((1<<PRTIM3)|(1<<PRUSART1)|(1<<PRUSB)); \
1481 }while(0)
1482 
1483 #define power_all_disable() \
1484 do{ \
1485  PRR0 |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)); \
1486  PRR1 |= (uint8_t)((1<<PRTIM3)|(1<<PRUSART1)|(1<<PRUSB)); \
1487 }while(0)
1488 
1489 
1490 #elif defined(__AVR_AT90PWM1__)
1491 
1492 #define power_adc_enable() (PRR &= (uint8_t)~(1 << PRADC))
1493 #define power_adc_disable() (PRR |= (uint8_t)(1 << PRADC))
1494 
1495 #define power_spi_enable() (PRR &= (uint8_t)~(1 << PRSPI))
1496 #define power_spi_disable() (PRR |= (uint8_t)(1 << PRSPI))
1497 
1498 #define power_timer0_enable() (PRR &= (uint8_t)~(1 << PRTIM0))
1499 #define power_timer0_disable() (PRR |= (uint8_t)(1 << PRTIM0))
1500 
1501 #define power_timer1_enable() (PRR &= (uint8_t)~(1 << PRTIM1))
1502 #define power_timer1_disable() (PRR |= (uint8_t)(1 << PRTIM1))
1503 
1504 /* Power Stage Controller 0 */
1505 #define power_psc0_enable() (PRR &= (uint8_t)~(1 << PRPSC0))
1506 #define power_psc0_disable() (PRR |= (uint8_t)(1 << PRPSC0))
1507 
1508 /* Power Stage Controller 1 */
1509 #define power_psc1_enable() (PRR &= (uint8_t)~(1 << PRPSC1))
1510 #define power_psc1_disable() (PRR |= (uint8_t)(1 << PRPSC1))
1511 
1512 /* Power Stage Controller 2 */
1513 #define power_psc2_enable() (PRR &= (uint8_t)~(1 << PRPSC2))
1514 #define power_psc2_disable() (PRR |= (uint8_t)(1 << PRPSC2))
1515 
1516 #define power_all_enable() (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRPSC0)|(1<<PRPSC1)|(1<<PRPSC2)))
1517 #define power_all_disable() (PRR |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRPSC0)|(1<<PRPSC1)|(1<<PRPSC2)))
1518 
1519 
1520 #elif defined(__AVR_AT90PWM2__) \
1521 || defined(__AVR_AT90PWM2B__) \
1522 || defined(__AVR_AT90PWM3__) \
1523 || defined(__AVR_AT90PWM3B__) \
1524 || defined(__AVR_AT90PWM216__) \
1525 || defined(__AVR_AT90PWM316__)
1526 
1527 #define power_adc_enable() (PRR &= (uint8_t)~(1 << PRADC))
1528 #define power_adc_disable() (PRR |= (uint8_t)(1 << PRADC))
1529 
1530 #define power_spi_enable() (PRR &= (uint8_t)~(1 << PRSPI))
1531 #define power_spi_disable() (PRR |= (uint8_t)(1 << PRSPI))
1532 
1533 #define power_usart_enable() (PRR &= (uint8_t)~(1 << PRUSART))
1534 #define power_usart_disable() (PRR |= (uint8_t)(1 << PRUSART))
1535 
1536 #define power_timer0_enable() (PRR &= (uint8_t)~(1 << PRTIM0))
1537 #define power_timer0_disable() (PRR |= (uint8_t)(1 << PRTIM0))
1538 
1539 #define power_timer1_enable() (PRR &= (uint8_t)~(1 << PRTIM1))
1540 #define power_timer1_disable() (PRR |= (uint8_t)(1 << PRTIM1))
1541 
1542 /* Power Stage Controller 0 */
1543 #define power_psc0_enable() (PRR &= (uint8_t)~(1 << PRPSC0))
1544 #define power_psc0_disable() (PRR |= (uint8_t)(1 << PRPSC0))
1545 
1546 /* Power Stage Controller 1 */
1547 #define power_psc1_enable() (PRR &= (uint8_t)~(1 << PRPSC1))
1548 #define power_psc1_disable() (PRR |= (uint8_t)(1 << PRPSC1))
1549 
1550 /* Power Stage Controller 2 */
1551 #define power_psc2_enable() (PRR &= (uint8_t)~(1 << PRPSC2))
1552 #define power_psc2_disable() (PRR |= (uint8_t)(1 << PRPSC2))
1553 
1554 #define power_all_enable() (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRPSC0)|(1<<PRPSC1)|(1<<PRPSC2)))
1555 #define power_all_disable() (PRR |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRPSC0)|(1<<PRPSC1)|(1<<PRPSC2)))
1556 
1557 
1558 #elif defined(__AVR_AT90PWM81__) \
1559 || defined(__AVR_AT90PWM161__)
1560 
1561 #define power_adc_enable() (PRR &= (uint8_t)~(1 << PRADC))
1562 #define power_adc_disable() (PRR |= (uint8_t)(1 << PRADC))
1563 
1564 #define power_spi_enable() (PRR &= (uint8_t)~(1 << PRSPI))
1565 #define power_spi_disable() (PRR |= (uint8_t)(1 << PRSPI))
1566 
1567 #define power_timer1_enable() (PRR &= (uint8_t)~(1 << PRTIM1))
1568 #define power_timer1_disable() (PRR |= (uint8_t)(1 << PRTIM1))
1569 
1570 /* Reduced Power Stage Controller */
1571 #define power_pscr_enable() (PRR &= (uint8_t)~(1 << PRPSCR))
1572 #define power_pscr_disable() (PRR |= (uint8_t)(1 << PRPSCR))
1573 
1574 /* Power Stage Controller 2 */
1575 #define power_psc2_enable() (PRR &= (uint8_t)~(1 << PRPSC2))
1576 #define power_psc2_disable() (PRR |= (uint8_t)(1 << PRPSC2))
1577 
1578 #define power_all_enable() (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRPSCR)|(1<<PRPSC2)))
1579 #define power_all_disable() (PRR |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRPSCR)|(1<<PRPSC2)))
1580 
1581 
1582 #elif defined(__AVR_ATmega165__) \
1583 || defined(__AVR_ATmega165A__) \
1584 || defined(__AVR_ATmega165P__) \
1585 || defined(__AVR_ATmega165PA__) \
1586 || defined(__AVR_ATmega325__) \
1587 || defined(__AVR_ATmega325A__) \
1588 || defined(__AVR_ATmega325PA__) \
1589 || defined(__AVR_ATmega3250__) \
1590 || defined(__AVR_ATmega3250A__) \
1591 || defined(__AVR_ATmega3250PA__) \
1592 || defined(__AVR_ATmega645__) \
1593 || defined(__AVR_ATmega645A__) \
1594 || defined(__AVR_ATmega645P__) \
1595 || defined(__AVR_ATmega6450__) \
1596 || defined(__AVR_ATmega6450A__) \
1597 || defined(__AVR_ATmega6450P__)
1598 
1599 #define power_adc_enable() (PRR &= (uint8_t)~(1 << PRADC))
1600 #define power_adc_disable() (PRR |= (uint8_t)(1 << PRADC))
1601 
1602 #define power_spi_enable() (PRR &= (uint8_t)~(1 << PRSPI))
1603 #define power_spi_disable() (PRR |= (uint8_t)(1 << PRSPI))
1604 
1605 #define power_usart0_enable() (PRR &= (uint8_t)~(1 << PRUSART0))
1606 #define power_usart0_disable() (PRR |= (uint8_t)(1 << PRUSART0))
1607 
1608 #define power_timer1_enable() (PRR &= (uint8_t)~(1 << PRTIM1))
1609 #define power_timer1_disable() (PRR |= (uint8_t)(1 << PRTIM1))
1610 
1611 #define power_all_enable() (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRTIM1)))
1612 #define power_all_disable() (PRR |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRTIM1)))
1613 
1614 
1615 #elif defined(__AVR_ATmega169__) \
1616 || defined(__AVR_ATmega169A__) \
1617 || defined(__AVR_ATmega169P__) \
1618 || defined(__AVR_ATmega169PA__) \
1619 || defined(__AVR_ATmega329__) \
1620 || defined(__AVR_ATmega329A__) \
1621 || defined(__AVR_ATmega329P__) \
1622 || defined(__AVR_ATmega329PA__) \
1623 || defined(__AVR_ATmega3290__) \
1624 || defined(__AVR_ATmega3290A__) \
1625 || defined(__AVR_ATmega3290P__) \
1626 || defined(__AVR_ATmega3290PA__) \
1627 || defined(__AVR_ATmega649__) \
1628 || defined(__AVR_ATmega649A__) \
1629 || defined(__AVR_ATmega649P__) \
1630 || defined(__AVR_ATmega6490__) \
1631 || defined(__AVR_ATmega6490A__) \
1632 || defined(__AVR_ATmega6490P__)
1633 
1634 #define power_adc_enable() (PRR &= (uint8_t)~(1 << PRADC))
1635 #define power_adc_disable() (PRR |= (uint8_t)(1 << PRADC))
1636 
1637 #define power_spi_enable() (PRR &= (uint8_t)~(1 << PRSPI))
1638 #define power_spi_disable() (PRR |= (uint8_t)(1 << PRSPI))
1639 
1640 #define power_usart0_enable() (PRR &= (uint8_t)~(1 << PRUSART0))
1641 #define power_usart0_disable() (PRR |= (uint8_t)(1 << PRUSART0))
1642 
1643 #define power_timer1_enable() (PRR &= (uint8_t)~(1 << PRTIM1))
1644 #define power_timer1_disable() (PRR |= (uint8_t)(1 << PRTIM1))
1645 
1646 #define power_lcd_enable() (PRR &= (uint8_t)~(1 << PRLCD))
1647 #define power_lcd_disable() (PRR |= (uint8_t)(1 << PRLCD))
1648 
1649 #define power_all_enable() (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRTIM1)|(1<<PRLCD)))
1650 #define power_all_disable() (PRR |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRTIM1)|(1<<PRLCD)))
1651 
1652 
1653 #elif defined(__AVR_ATmega164A__) \
1654 || defined(__AVR_ATmega164P__) \
1655 || defined(__AVR_ATmega324A__) \
1656 || defined(__AVR_ATmega324P__) \
1657 || defined(__AVR_ATmega324PA__) \
1658 || defined(__AVR_ATmega644P__) \
1659 || defined(__AVR_ATmega644A__) \
1660 || defined(__AVR_ATmega644PA__)
1661 
1662 #define power_adc_enable() (PRR0 &= (uint8_t)~(1 << PRADC))
1663 #define power_adc_disable() (PRR0 |= (uint8_t)(1 << PRADC))
1664 
1665 #define power_spi_enable() (PRR0 &= (uint8_t)~(1 << PRSPI))
1666 #define power_spi_disable() (PRR0 |= (uint8_t)(1 << PRSPI))
1667 
1668 #define power_usart0_enable() (PRR0 &= (uint8_t)~(1 << PRUSART0))
1669 #define power_usart0_disable() (PRR0 |= (uint8_t)(1 << PRUSART0))
1670 
1671 #define power_usart1_enable() (PRR0 &= (uint8_t)~(1 << PRUSART1))
1672 #define power_usart1_disable() (PRR0 |= (uint8_t)(1 << PRUSART1))
1673 
1674 #define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRTIM0))
1675 #define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRTIM0))
1676 
1677 #define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRTIM1))
1678 #define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRTIM1))
1679 
1680 #define power_timer2_enable() (PRR0 &= (uint8_t)~(1 << PRTIM2))
1681 #define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRTIM2))
1682 
1683 #define power_twi_enable() (PRR0 &= (uint8_t)~(1 << PRTWI))
1684 #define power_twi_disable() (PRR0 |= (uint8_t)(1 << PRTWI))
1685 
1686 #define power_all_enable() (PRR0 &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRUSART1)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRTWI)))
1687 #define power_all_disable() (PRR0 |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRUSART1)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRTWI)))
1688 
1689 
1690 #elif defined(__AVR_ATmega644__) \
1691 || defined(__AVR_ATmega164PA__)
1692 
1693 #define power_adc_enable() (PRR0 &= (uint8_t)~(1 << PRADC))
1694 #define power_adc_disable() (PRR0 |= (uint8_t)(1 << PRADC))
1695 
1696 #define power_spi_enable() (PRR0 &= (uint8_t)~(1 << PRSPI))
1697 #define power_spi_disable() (PRR0 |= (uint8_t)(1 << PRSPI))
1698 
1699 #define power_usart0_enable() (PRR0 &= (uint8_t)~(1 << PRUSART0))
1700 #define power_usart0_disable() (PRR0 |= (uint8_t)(1 << PRUSART0))
1701 
1702 #define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRTIM0))
1703 #define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRTIM0))
1704 
1705 #define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRTIM1))
1706 #define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRTIM1))
1707 
1708 #define power_timer2_enable() (PRR0 &= (uint8_t)~(1 << PRTIM2))
1709 #define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRTIM2))
1710 
1711 #define power_twi_enable() (PRR0 &= (uint8_t)~(1 << PRTWI))
1712 #define power_twi_disable() (PRR0 |= (uint8_t)(1 << PRTWI))
1713 
1714 #define power_all_enable() (PRR0 &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRTWI)))
1715 #define power_all_disable() (PRR0 |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRTWI)))
1716 
1717 
1718 #elif defined(__AVR_ATmega406__)
1719 
1720 #define power_twi_enable() (PRR0 &= (uint8_t)~(1 << PRTWI))
1721 #define power_twi_disable() (PRR0 |= (uint8_t)(1 << PRTWI))
1722 
1723 #define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRTIM0))
1724 #define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRTIM0))
1725 
1726 #define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRTIM1))
1727 #define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRTIM1))
1728 
1729 /* Voltage ADC */
1730 #define power_vadc_enable() (PRR0 &= (uint8_t)~(1 << PRVADC))
1731 #define power_vadc_disable() (PRR0 |= (uint8_t)(1 << PRVADC))
1732 
1733 #define power_all_enable() (PRR0 &= (uint8_t)~((1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRVADC)))
1734 #define power_all_disable() (PRR0 |= (uint8_t)((1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRVADC)))
1735 
1736 
1737 #elif defined(__AVR_ATmega48__) \
1738 || defined(__AVR_ATmega48A__) \
1739 || defined(__AVR_ATmega48PA__) \
1740 || defined(__AVR_ATmega48P__) \
1741 || defined(__AVR_ATmega88__) \
1742 || defined(__AVR_ATmega88A__) \
1743 || defined(__AVR_ATmega88P__) \
1744 || defined(__AVR_ATmega88PA__) \
1745 || defined(__AVR_ATmega168__) \
1746 || defined(__AVR_ATmega168A__) \
1747 || defined(__AVR_ATmega168P__) \
1748 || defined(__AVR_ATmega168PA__) \
1749 || defined(__AVR_ATmega328__) \
1750 || defined(__AVR_ATmega328P__) \
1751 || defined(__AVR_ATtiny48__) \
1752 || defined(__AVR_ATtiny88__) \
1753 || defined(__AVR_ATtiny828__)
1754 
1755 #define power_adc_enable() (PRR &= (uint8_t)~(1 << PRADC))
1756 #define power_adc_disable() (PRR |= (uint8_t)(1 << PRADC))
1757 
1758 #define power_spi_enable() (PRR &= (uint8_t)~(1 << PRSPI))
1759 #define power_spi_disable() (PRR |= (uint8_t)(1 << PRSPI))
1760 
1761 #define power_usart0_enable() (PRR &= (uint8_t)~(1 << PRUSART0))
1762 #define power_usart0_disable() (PRR |= (uint8_t)(1 << PRUSART0))
1763 
1764 #define power_timer0_enable() (PRR &= (uint8_t)~(1 << PRTIM0))
1765 #define power_timer0_disable() (PRR |= (uint8_t)(1 << PRTIM0))
1766 
1767 #define power_timer1_enable() (PRR &= (uint8_t)~(1 << PRTIM1))
1768 #define power_timer1_disable() (PRR |= (uint8_t)(1 << PRTIM1))
1769 
1770 #if !defined(__AVR_ATtiny828__)
1771 
1772 #define power_timer2_enable() (PRR &= (uint8_t)~(1 << PRTIM2))
1773 #define power_timer2_disable() (PRR |= (uint8_t)(1 << PRTIM2))
1774 
1775 #endif
1776 
1777 #define power_twi_enable() (PRR &= (uint8_t)~(1 << PRTWI))
1778 #define power_twi_disable() (PRR |= (uint8_t)(1 << PRTWI))
1779 
1780 #if defined(__AVR_ATtiny828__)
1781 
1782 #define power_all_enable() (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTWI)))
1783 #define power_all_disable() (PRR |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTWI)))
1784 
1785 #else
1786 
1787 #define power_all_enable() (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRTWI)))
1788 #define power_all_disable() (PRR |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRTWI)))
1789 
1790 #endif
1791 
1792 #elif defined(__AVR_ATtiny24__) \
1793 || defined(__AVR_ATtiny24A__) \
1794 || defined(__AVR_ATtiny44__) \
1795 || defined(__AVR_ATtiny44A__) \
1796 || defined(__AVR_ATtiny84__) \
1797 || defined(__AVR_ATtiny84A__) \
1798 || defined(__AVR_ATtiny25__) \
1799 || defined(__AVR_ATtiny45__) \
1800 || defined(__AVR_ATtiny85__) \
1801 || defined(__AVR_ATtiny261__) \
1802 || defined(__AVR_ATtiny261A__) \
1803 || defined(__AVR_ATtiny461__) \
1804 || defined(__AVR_ATtiny461A__) \
1805 || defined(__AVR_ATtiny861__) \
1806 || defined(__AVR_ATtiny861A__) \
1807 || defined(__AVR_ATtiny43U__)
1808 
1809 #define power_adc_enable() (PRR &= (uint8_t)~(1 << PRADC))
1810 #define power_adc_disable() (PRR |= (uint8_t)(1 << PRADC))
1811 
1812 #define power_timer0_enable() (PRR &= (uint8_t)~(1 << PRTIM0))
1813 #define power_timer0_disable() (PRR |= (uint8_t)(1 << PRTIM0))
1814 
1815 #define power_timer1_enable() (PRR &= (uint8_t)~(1 << PRTIM1))
1816 #define power_timer1_disable() (PRR |= (uint8_t)(1 << PRTIM1))
1817 
1818 /* Universal Serial Interface */
1819 #define power_usi_enable() (PRR &= (uint8_t)~(1 << PRUSI))
1820 #define power_usi_disable() (PRR |= (uint8_t)(1 << PRUSI))
1821 
1822 #define power_all_enable() (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRUSI)))
1823 #define power_all_disable() (PRR |= (uint8_t)((1<<PRADC)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRUSI)))
1824 
1825 #elif defined(__AVR_ATmega1284__)
1826 
1827 #define power_adc_enable() (PRR0 &= (uint8_t)~(1 << PRADC))
1828 #define power_adc_disable() (PRR0 |= (uint8_t)(1 << PRADC))
1829 
1830 #define power_spi_enable() (PRR0 &= (uint8_t)~(1 << PRSPI))
1831 #define power_spi_disable() (PRR0 |= (uint8_t)(1 << PRSPI))
1832 
1833 #define power_twi_enable() (PRR0 &= (uint8_t)~(1 << PRTWI))
1834 #define power_twi_disable() (PRR0 |= (uint8_t)(1 << PRTWI))
1835 
1836 #define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRTIM0))
1837 #define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRTIM0))
1838 
1839 #define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRTIM1))
1840 #define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRTIM1))
1841 
1842 #define power_timer2_enable() (PRR0 &= (uint8_t)~(1 << PRTIM2))
1843 #define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRTIM2))
1844 
1845 #define power_timer3_enable() (PRR1 &= (uint8_t)~(1 << PRTIM3))
1846 #define power_timer3_disable() (PRR1 |= (uint8_t)(1 << PRTIM3))
1847 
1848 #define power_usart0_enable() (PRR0 &= (uint8_t)~(1 << PRUSART0))
1849 #define power_usart0_disable() (PRR0 |= (uint8_t)(1 << PRUSART0))
1850 
1851 #define power_all_enable() \
1852 do{ \
1853  PRR0 &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRUSART0)); \
1854  PRR1 &= (uint8_t)~(1<<PRTIM3); \
1855 }while(0)
1856 
1857 #define power_all_disable() \
1858 do{ \
1859  PRR0 |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRUSART0)); \
1860  PRR1 |= (uint8_t)(1<<PRTIM3); \
1861 }while(0)
1862 
1863 #elif defined(__AVR_ATmega1284P__)
1864 
1865 
1866 #define power_adc_enable() (PRR0 &= (uint8_t)~(1 << PRADC))
1867 #define power_adc_disable() (PRR0 |= (uint8_t)(1 << PRADC))
1868 
1869 #define power_spi_enable() (PRR0 &= (uint8_t)~(1 << PRSPI))
1870 #define power_spi_disable() (PRR0 |= (uint8_t)(1 << PRSPI))
1871 
1872 #define power_twi_enable() (PRR0 &= (uint8_t)~(1 << PRTWI))
1873 #define power_twi_disable() (PRR0 |= (uint8_t)(1 << PRTWI))
1874 
1875 #define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRTIM0))
1876 #define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRTIM0))
1877 
1878 #define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRTIM1))
1879 #define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRTIM1))
1880 
1881 #define power_timer2_enable() (PRR0 &= (uint8_t)~(1 << PRTIM2))
1882 #define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRTIM2))
1883 
1884 #define power_timer3_enable() (PRR1 &= (uint8_t)~(1 << PRTIM3))
1885 #define power_timer3_disable() (PRR1 |= (uint8_t)(1 << PRTIM3))
1886 
1887 #define power_usart0_enable() (PRR0 &= (uint8_t)~(1 << PRUSART0))
1888 #define power_usart0_disable() (PRR0 |= (uint8_t)(1 << PRUSART0))
1889 
1890 #define power_usart1_enable() (PRR0 &= (uint8_t)~(1 << PRUSART1))
1891 #define power_usart1_disable() (PRR0 |= (uint8_t)(1 << PRUSART1))
1892 
1893 #define power_all_enable() \
1894 do{ \
1895  PRR0 &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRUSART0)|(1<<PRUSART1)); \
1896  PRR1 &= (uint8_t)~(1<<PRTIM3); \
1897 }while(0)
1898 
1899 #define power_all_disable() \
1900 do{ \
1901  PRR0 |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRUSART0)|(1<<PRUSART1)); \
1902  PRR1 |= (uint8_t)(1<<PRTIM3); \
1903 }while(0)
1904 
1905 
1906 #elif defined(__AVR_ATmega32HVB__) \
1907 || defined(__AVR_ATmega32HVBREVB__) \
1908 || defined(__AVR_ATmega16HVB__) \
1909 || defined(__AVR_ATmega16HVBREVB__)
1910 
1911 
1912 #define power_twi_enable() (PRR0 &= (uint8_t)~(1 << PRTWI))
1913 #define power_twi_disable() (PRR0 |= (uint8_t)(1 << PRTWI))
1914 
1915 #define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRTIM0))
1916 #define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRTIM0))
1917 
1918 #define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRTIM1))
1919 #define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRTIM1))
1920 
1921 /* Voltage ADC */
1922 #define power_vadc_enable() (PRR0 &= (uint8_t)~(1 << PRVADC))
1923 #define power_vadc_disable() (PRR0 |= (uint8_t)(1 << PRVADC))
1924 
1925 #define power_spi_enable() (PRR0 &= (uint8_t)~(1 << PRSPI))
1926 #define power_spi_disable() (PRR0 |= (uint8_t)(1 << PRSPI))
1927 
1928 #define power_vrm_enable() (PRR0 &= (uint8_t)~(1 << PRVRM))
1929 #define power_vrm_disable() (PRR0 |= (uint8_t)(1 << PRVRM))
1930 
1931 #define power_all_enable() (PRR0 &= (uint8_t)~((1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRVADC)|(1<<PRSPI)|(1<<PRVRM)))
1932 #define power_all_disable() (PRR0 |= (uint8_t)((1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRVADC)|(1<<PRSPI)|(1<<PRVRM)))
1933 
1934 
1935 #elif defined (__AVR_ATA5790__) \
1936 || defined (__AVR_ATA5795__)
1937 
1938 // Enable the voltage monitor
1939 #define power_vmonitor_enable() (PRR0 &= (uint8_t)~(1 << PRVM))
1940 #define power_vmonitor_disable() (PRR0 |= (uint8_t)(1 << PRVM))
1941 
1942 #define power_irdriver_enable() (PRR0 &= (uint8_t)~(1 << PRDS))
1943 #define power_irdriver_disable() (PRR0 |= (uint8_t)(1 << PRDS))
1944 
1945 #define power_crypto_enable() (PRR0 &= (uint8_t)~(1 << PRCU))
1946 #define power_crypto_disable() (PRR0 |= (uint8_t)(1 << PRCU))
1947 
1948 #define power_timermodulator_enable() (PRR0 &= (uint8_t)~(1 << PRTM))
1949 #define power_timermodulator_disable() (PRR0 |= (uint8_t)(1 << PRTM))
1950 
1951 #define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRT1))
1952 #define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRT1))
1953 
1954 #define power_timer2_enable() (PRR0 &= (uint8_t)~(1 << PRT2))
1955 #define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRT2))
1956 
1957 #define power_timer3_enable() (PRR0 &= (uint8_t)~(1 << PRT3))
1958 #define power_timer3_disable() (PRR0 |= (uint8_t)(1 << PRT3))
1959 
1960 #define power_spi_enable() (PRR1 &= (uint8_t)~(1 << PRSPI))
1961 #define power_spi_disable() (PRR1 |= (uint8_t)(1 << PRSPI))
1962 
1963 #define power_cinterface_enable() (PRR1 &= (uint8_t)~(1 << PRCI))
1964 #define power_cinterface_disable() (PRR1 |= (uint8_t)(1 << PRCI))
1965 
1966 #if defined(__AVR_ATA5790__)
1967 
1968 #define power_lfreceiver_enable() (PRR0 &= (uint8_t)~(1 << PRLFR))
1969 #define power_lfreceiver_disable() (PRR0 |= (uint8_t)(1 << PRLFR))
1970 
1971 #define power_all_enable() \
1972 do{ \
1973  PRR0 &= (uint8_t)~((1<<PRVM)|(1<<PRDS)|(1<<PRCU)|(1<<PRTM)|(1<<PRT3)|(1<<PRT2)|(1<<PRT1)|(1<<PRLFR)); \
1974  PRR1 &= (uint8_t)~((1<<PRSPI)|(1<<PRCI)); \
1975 }while(0)
1976 
1977 #define power_all_disable() \
1978 do{ \
1979  PRR0 |= (uint8_t)((1<<PRVM)|(1<<PRDS)|(1<<PRCU)|(1<<PRTM)|(1<<PRT3)|(1<<PRT2)|(1<<PRT1)|(1<<PRLFR)); \
1980  PRR1 |= (uint8_t)((1<<PRSPI)|(1<<PRCI)); \
1981 }while(0)
1982 
1983 #elif defined(__AVR_ATA5795__)
1984 
1985 #define power_all_enable() \
1986 do{ \
1987  PRR0 &= (uint8_t)~((1<<PRVM)|(1<<PRDS)|(1<<PRCU)|(1<<PRTM)|(1<<PRT3)|(1<<PRT2)|(1<<PRT1)); \
1988  PRR1 &= (uint8_t)~((1<<PRSPI)|(1<<PRCI)); \
1989 }while(0)
1990 
1991 #define power_all_disable() \
1992 do{ \
1993  PRR0 |= (uint8_t)((1<<PRVM)|(1<<PRDS)|(1<<PRCU)|(1<<PRTM)|(1<<PRT3)|(1<<PRT2)|(1<<PRT1)); \
1994  PRR1 |= (uint8_t)((1<<PRSPI)|(1<<PRCI)); \
1995 }while(0)
1996 
1997 #endif
1998 
1999 #elif defined(__AVR_ATmega16M1__) \
2000 || defined(__AVR_ATmega32C1__) \
2001 || defined(__AVR_ATmega32M1__) \
2002 || defined(__AVR_ATmega64C1__) \
2003 || defined(__AVR_ATmega64M1__)
2004 
2005 #define power_adc_enable() (PRR &= (uint8_t)~(1 << PRADC))
2006 #define power_adc_disable() (PRR |= (uint8_t)(1 << PRADC))
2007 
2008 #define power_lin_enable() (PRR &= (uint8_t)~(1 << PRLIN))
2009 #define power_lin_disable() (PRR |= (uint8_t)(1 << PRLIN))
2010 
2011 #define power_spi_enable() (PRR &= (uint8_t)~(1 << PRSPI))
2012 #define power_spi_disable() (PRR |= (uint8_t)(1 << PRSPI))
2013 
2014 #define power_timer0_enable() (PRR &= (uint8_t)~(1 << PRTIM0))
2015 #define power_timer0_disable() (PRR |= (uint8_t)(1 << PRTIM0))
2016 
2017 #define power_timer1_enable() (PRR &= (uint8_t)~(1 << PRTIM1))
2018 #define power_timer1_disable() (PRR |= (uint8_t)(1 << PRTIM1))
2019 
2020 #define power_psc_enable() (PRR &= (uint8_t)~(1 << PRPSC))
2021 #define power_psc_disable() (PRR |= (uint8_t)(1 << PRPSC))
2022 
2023 #define power_can_enable() (PRR &= (uint8_t)~(1 << PRCAN))
2024 #define power_can_disable() (PRR |= (uint8_t)(1 << PRCAN))
2025 
2026 #define power_all_enable() (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRLIN)|(1<<PRSPI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRPSC)|(1<<PRCAN)))
2027 #define power_all_disable() (PRR |= (uint8_t)((1<<PRADC)|(1<<PRLIN)|(1<<PRSPI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRPSC)|(1<<PRCAN)))
2028 
2029 
2030 #elif defined(__AVR_ATtiny167__) \
2031 || defined(__AVR_ATtiny87__) \
2032 || defined(__AVR_ATA5505__) \
2033 || defined(__AVR_ATA5272__)
2034 
2035 #define power_adc_enable() (PRR &= (uint8_t)~(1 << PRADC))
2036 #define power_adc_disable() (PRR |= (uint8_t)(1 << PRADC))
2037 
2038 #define power_usi_enable() (PRR &= (uint8_t)~(1 << PRUSI))
2039 #define power_usi_disable() (PRR |= (uint8_t)(1 << PRUSI))
2040 
2041 #define power_timer0_enable() (PRR &= (uint8_t)~(1 << PRTIM0))
2042 #define power_timer0_disable() (PRR |= (uint8_t)(1 << PRTIM0))
2043 
2044 #define power_timer1_enable() (PRR &= (uint8_t)~(1 << PRTIM1))
2045 #define power_timer1_disable() (PRR |= (uint8_t)(1 << PRTIM1))
2046 
2047 #define power_spi_enable() (PRR &= (uint8_t)~(1 << PRSPI))
2048 #define power_spi_disable() (PRR |= (uint8_t)(1 << PRSPI))
2049 
2050 #define power_lin_enable() (PRR &= (uint8_t)~(1 << PRLIN))
2051 #define power_lin_disable() (PRR |= (uint8_t)(1 << PRLIN))
2052 
2053 #define power_all_enable() (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRLIN)))
2054 #define power_all_disable() (PRR |= (uint8_t)((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRLIN)))
2055 
2056 
2057 #elif defined(__AVR_ATtiny1634__)
2058 
2059 #define power_adc_enable() (PRR &= (uint8_t)~(1 << PRADC))
2060 #define power_adc_disable() (PRR |= (uint8_t)(1 << PRADC))
2061 
2062 #define power_usart0_enable() (PRR &= (uint8_t)~(1 << PRUSART0))
2063 #define power_usart0_disable() (PRR |= (uint8_t)(1 << PRUSART0))
2064 
2065 #define power_usart1_enable() (PRR &= (uint8_t)~(1 << PRUSART1))
2066 #define power_usart1_disable() (PRR |= (uint8_t)(1 << PRUSART1))
2067 
2068 #define power_usi_enable() (PRR &= (uint8_t)~(1 << PRUSI))
2069 #define power_usi_disable() (PRR |= (uint8_t)(1 << PRUSI))
2070 
2071 #define power_timer0_enable() (PRR &= (uint8_t)~(1 << PRTIM0))
2072 #define power_timer0_disable() (PRR |= (uint8_t)(1 << PRTIM0))
2073 
2074 #define power_timer1_enable() (PRR &= (uint8_t)~(1 << PRTIM1))
2075 #define power_timer1_disable() (PRR |= (uint8_t)(1 << PRTIM1))
2076 
2077 #define power_twi_enable() (PRR &= (uint8_t)~(1 << PRTWI))
2078 #define power_twi_disable() (PRR |= (uint8_t)(1 << PRTWI))
2079 
2080 #define power_all_enable() (PRR &= (uint8_t)~((1 << PRTWI)|(1 << PRUSI)|(1 << PRTIM0)|(1 << PRTIM1)|(1 << PRUSART0)|(1 << PRUSART1)|(1 << PRADC)))
2081 #define power_all_disable() (PRR |= (uint8_t)((1 << PRTWI)|(1 << PRUSI)|(1 << PRTIM0)|(1 << PRTIM1)|(1 << PRUSART0)|(1 << PRUSART1)|(1 << PRADC)))
2082 
2083 
2084 #elif defined(__AVR_AT90USB82__) \
2085 || defined(__AVR_AT90USB162__) \
2086 || defined(__AVR_ATmega8U2__) \
2087 || defined(__AVR_ATmega16U2__) \
2088 || defined(__AVR_ATmega32U2__)
2089 
2090 #define power_spi_enable() (PRR0 &= (uint8_t)~(1 << PRSPI))
2091 #define power_spi_disable() (PRR0 |= (uint8_t)(1 << PRSPI))
2092 
2093 #define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRTIM0))
2094 #define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRTIM0))
2095 
2096 #define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRTIM1))
2097 #define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRTIM1))
2098 
2099 #define power_usb_enable() (PRR1 &= (uint8_t)~(1 << PRUSB))
2100 #define power_usb_disable() (PRR1 |= (uint8_t)(1 << PRUSB))
2101 
2102 #define power_usart1_enable() (PRR1 &= (uint8_t)~(1 << PRUSART1))
2103 #define power_usart1_disable() (PRR1 |= (uint8_t)(1 << PRUSART1))
2104 
2105 #define power_all_enable() \
2106 do{ \
2107  PRR0 &= (uint8_t)~((1<<PRSPI)|(1<<PRTIM0)|(1<<PRTIM1)); \
2108  PRR1 &= (uint8_t)~((1<<PRUSB)|(1<<PRUSART1)); \
2109 }while(0)
2110 
2111 #define power_all_disable() \
2112 do{ \
2113  PRR0 |= (uint8_t)((1<<PRSPI)|(1<<PRTIM0)|(1<<PRTIM1)); \
2114  PRR1 |= (uint8_t)((1<<PRUSB)|(1<<PRUSART1)); \
2115 }while(0)
2116 
2117 
2118 #elif defined(__AVR_AT90SCR100__)
2119 
2120 #define power_usart0_enable() (PRR0 &= (uint8_t)~(1 << PRUSART0))
2121 #define power_usart0_disable() (PRR0 |= (uint8_t)(1 << PRUSART0))
2122 
2123 #define power_spi_enable() (PRR0 &= (uint8_t)~(1 << PRSPI))
2124 #define power_spi_disable() (PRR0 |= (uint8_t)(1 << PRSPI))
2125 
2126 #define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRTIM1))
2127 #define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRTIM1))
2128 
2129 #define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRTIM0))
2130 #define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRTIM0))
2131 
2132 #define power_timer2_enable() (PRR0 &= (uint8_t)~(1 << PRTIM2))
2133 #define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRTIM2))
2134 
2135 #define power_twi_enable() (PRR0 &= (uint8_t)~(1 << PRTWI))
2136 #define power_twi_disable() (PRR0 |= (uint8_t)(1 << PRTWI))
2137 
2138 #define power_usbh_enable() (PRR1 &= (uint8_t)~(1 << PRUSBH))
2139 #define power_usbh_disable() (PRR1 |= (uint8_t)(1 << PRUSBH))
2140 
2141 #define power_usb_enable() (PRR1 &= (uint8_t)~(1 << PRUSB))
2142 #define power_usb_disable() (PRR1 |= (uint8_t)(1 << PRUSB))
2143 
2144 #define power_hsspi_enable() (PRR1 &= (uint8_t)~(1 << PRHSSPI))
2145 #define power_hsspi_disable() (PRR1 |= (uint8_t)(1 << PRHSSPI))
2146 
2147 #define power_sci_enable() (PRR1 &= (uint8_t)~(1 << PRSCI))
2148 #define power_sci_disable() (PRR1 |= (uint8_t)(1 << PRSCI))
2149 
2150 #define power_aes_enable() (PRR1 &= (uint8_t)~(1 << PRAES))
2151 #define power_aes_disable() (PRR1 |= (uint8_t)(1 << PRAES))
2152 
2153 #define power_kb_enable() (PRR1 &= (uint8_t)~(1 << PRKB))
2154 #define power_kb_disable() (PRR1 |= (uint8_t)(1 << PRKB))
2155 
2156 #define power_all_enable() \
2157 do{ \
2158  PRR0 &= (uint8_t)~((1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI)); \
2159  PRR1 &= (uint8_t)~((1<<PRUSBH)|(1<<PRUSB)|(1<<PRHSSPI)|(1<<PRSCI)|(1<<PRAES)|(1<<PRKB)); \
2160 }while(0)
2161 
2162 #define power_all_disable() \
2163 do{ \
2164  PRR0 |= (uint8_t)((1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI)); \
2165  PRR1 |= (uint8_t)((1<<PRUSBH)|(1<<PRUSB)|(1<<PRHSSPI)|(1<<PRSCI)|(1<<PRAES)|(1<<PRKB)); \
2166 }while(0)
2167 
2168 
2169 #elif defined(__AVR_ATtiny4__) \
2170 || defined(__AVR_ATtiny5__) \
2171 || defined(__AVR_ATtiny9__) \
2172 || defined(__AVR_ATtiny10__) \
2173 || defined(__AVR_ATtiny13A__) \
2174 
2175 #define power_adc_enable() (PRR &= (uint8_t)~(1 << PRADC))
2176 #define power_adc_disable() (PRR |= (uint8_t)(1 << PRADC))
2177 
2178 #define power_timer0_enable() (PRR &= (uint8_t)~(1 << PRTIM0))
2179 #define power_timer0_disable() (PRR |= (uint8_t)(1 << PRTIM0))
2180 
2181 #define power_all_enable() (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRTIM0)))
2182 #define power_all_disable() (PRR |= (uint8_t)((1<<PRADC)|(1<<PRTIM0)))
2183 
2184 
2185 #elif defined(__AVR_ATtiny20__) \
2186 || defined(__AVR_ATtiny40__)
2187 
2188 #define power_adc_enable() (PRR &= (uint8_t)~(1 << PRADC))
2189 #define power_adc_disable() (PRR |= (uint8_t)(1 << PRADC))
2190 
2191 #define power_timer0_enable() (PRR &= (uint8_t)~(1 << PRTIM0))
2192 #define power_timer0_disable() (PRR |= (uint8_t)(1 << PRTIM0))
2193 
2194 #define power_timer1_enable() (PRR &= (uint8_t)~(1 << PRTIM1))
2195 #define power_timer1_disable() (PRR |= (uint8_t)(1 << PRTIM1))
2196 
2197 #define power_spi_enable() (PRR &= (uint8_t)~(1 << PRSPI))
2198 #define power_spi_disable() (PRR |= (uint8_t)(1 << PRSPI))
2199 
2200 #define power_twi_enable() (PRR &= (uint8_t)~(1 << PRTWI))
2201 #define power_twi_disable() (PRR |= (uint8_t)(1 << PRTWI))
2202 
2203 #define power_all_enable() (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRTWI)))
2204 #define power_all_disable() (PRR |= (uint8_t)((1<<PRADC)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRTWI)))
2205 
2206 #endif
2207 
2208 
2209 #if defined(__AVR_AT90CAN32__) \
2210 || defined(__AVR_AT90CAN64__) \
2211 || defined(__AVR_AT90CAN128__) \
2212 || defined(__AVR_AT90PWM1__) \
2213 || defined(__AVR_AT90PWM2__) \
2214 || defined(__AVR_AT90PWM2B__) \
2215 || defined(__AVR_AT90PWM3__) \
2216 || defined(__AVR_AT90PWM3B__) \
2217 || defined(__AVR_AT90PWM81__) \
2218 || defined(__AVR_AT90PWM161__) \
2219 || defined(__AVR_AT90PWM216__) \
2220 || defined(__AVR_AT90PWM316__) \
2221 || defined(__AVR_AT90SCR100__) \
2222 || defined(__AVR_AT90USB646__) \
2223 || defined(__AVR_AT90USB647__) \
2224 || defined(__AVR_AT90USB82__) \
2225 || defined(__AVR_AT90USB1286__) \
2226 || defined(__AVR_AT90USB1287__) \
2227 || defined(__AVR_AT90USB162__) \
2228 || defined(__AVR_ATA5505__) \
2229 || defined(__AVR_ATA5272__) \
2230 || defined(__AVR_ATmega1280__) \
2231 || defined(__AVR_ATmega1281__) \
2232 || defined(__AVR_ATmega1284__) \
2233 || defined(__AVR_ATmega128RFA1__) \
2234 || defined(__AVR_ATmega1284RFR2__) \
2235 || defined(__AVR_ATmega128RFR2__) \
2236 || defined(__AVR_ATmega1284P__) \
2237 || defined(__AVR_ATmega162__) \
2238 || defined(__AVR_ATmega164A__) \
2239 || defined(__AVR_ATmega164P__) \
2240 || defined(__AVR_ATmega164PA__) \
2241 || defined(__AVR_ATmega165__) \
2242 || defined(__AVR_ATmega165A__) \
2243 || defined(__AVR_ATmega165P__) \
2244 || defined(__AVR_ATmega165PA__) \
2245 || defined(__AVR_ATmega168__) \
2246 || defined(__AVR_ATmega168P__) \
2247 || defined(__AVR_ATmega168PA__) \
2248 || defined(__AVR_ATmega169__) \
2249 || defined(__AVR_ATmega169A__) \
2250 || defined(__AVR_ATmega169P__) \
2251 || defined(__AVR_ATmega169PA__) \
2252 || defined(__AVR_ATmega16U4__) \
2253 || defined(__AVR_ATmega2560__) \
2254 || defined(__AVR_ATmega2561__) \
2255 || defined(__AVR_ATmega2564RFR2__) \
2256 || defined(__AVR_ATmega256RFR2__) \
2257 || defined(__AVR_ATmega324A__) \
2258 || defined(__AVR_ATmega324P__) \
2259 || defined(__AVR_ATmega325__) \
2260 || defined(__AVR_ATmega325A__) \
2261 || defined(__AVR_ATmega325PA__) \
2262 || defined(__AVR_ATmega3250__) \
2263 || defined(__AVR_ATmega3250A__) \
2264 || defined(__AVR_ATmega3250PA__) \
2265 || defined(__AVR_ATmega328__) \
2266 || defined(__AVR_ATmega328P__) \
2267 || defined(__AVR_ATmega329__) \
2268 || defined(__AVR_ATmega329A__) \
2269 || defined(__AVR_ATmega329P__) \
2270 || defined(__AVR_ATmega329PA__) \
2271 || defined(__AVR_ATmega3290__) \
2272 || defined(__AVR_ATmega3290A__) \
2273 || defined(__AVR_ATmega3290PA__) \
2274 || defined(__AVR_ATmega32C1__) \
2275 || defined(__AVR_ATmega32M1__) \
2276 || defined(__AVR_ATmega32U2__) \
2277 || defined(__AVR_ATmega32U4__) \
2278 || defined(__AVR_ATmega32U6__) \
2279 || defined(__AVR_ATmega48__) \
2280 || defined(__AVR_ATmega48A__) \
2281 || defined(__AVR_ATmega48PA__) \
2282 || defined(__AVR_ATmega48P__) \
2283 || defined(__AVR_ATmega640__) \
2284 || defined(__AVR_ATmega649P__) \
2285 || defined(__AVR_ATmega644__) \
2286 || defined(__AVR_ATmega644A__) \
2287 || defined(__AVR_ATmega644P__) \
2288 || defined(__AVR_ATmega644PA__) \
2289 || defined(__AVR_ATmega645__) \
2290 || defined(__AVR_ATmega645A__) \
2291 || defined(__AVR_ATmega645P__) \
2292 || defined(__AVR_ATmega6450__) \
2293 || defined(__AVR_ATmega6450A__) \
2294 || defined(__AVR_ATmega6450P__) \
2295 || defined(__AVR_ATmega649__) \
2296 || defined(__AVR_ATmega649A__) \
2297 || defined(__AVR_ATmega6490__) \
2298 || defined(__AVR_ATmega6490A__) \
2299 || defined(__AVR_ATmega6490P__) \
2300 || defined(__AVR_ATmega644RFR2__) \
2301 || defined(__AVR_ATmega64RFR2__) \
2302 || defined(__AVR_ATmega88__) \
2303 || defined(__AVR_ATmega88P__) \
2304 || defined(__AVR_ATmega8U2__) \
2305 || defined(__AVR_ATmega16U2__) \
2306 || defined(__AVR_ATmega32U2__) \
2307 || defined(__AVR_ATtiny48__) \
2308 || defined(__AVR_ATtiny167__) \
2309 || defined(__DOXYGEN__)
2310 
2311 
2312 /** \addtogroup avr_power
2313 
2314 Some of the newer AVRs contain a System Clock Prescale Register (CLKPR) that
2315 allows you to decrease the system clock frequency and the power consumption
2316 when the need for processing power is low.
2317 On some earlier AVRs (ATmega103, ATmega64, ATmega128), similar
2318 functionality can be achieved through the XTAL Divide Control Register.
2319 Below are two macros and an enumerated type that can be used to
2320 interface to the Clock Prescale Register or
2321 XTAL Divide Control Register.
2322 
2323 \note Not all AVR devices have a clock prescaler. On those devices
2324 without a Clock Prescale Register or XTAL Divide Control Register, these
2325 macros are not available.
2326 */
2327 
2328 
2329 /** \addtogroup avr_power
2330 \code
2331 typedef enum
2332 {
2333  clock_div_1 = 0,
2334  clock_div_2 = 1,
2335  clock_div_4 = 2,
2336  clock_div_8 = 3,
2337  clock_div_16 = 4,
2338  clock_div_32 = 5,
2339  clock_div_64 = 6,
2340  clock_div_128 = 7,
2341  clock_div_256 = 8,
2342  clock_div_1_rc = 15, // ATmega128RFA1 only
2343 } clock_div_t;
2344 \endcode
2345 Clock prescaler setting enumerations for device using
2346 System Clock Prescale Register.
2347 
2348 \code
2349 typedef enum
2350 {
2351  clock_div_1 = 1,
2352  clock_div_2 = 2,
2353  clock_div_4 = 4,
2354  clock_div_8 = 8,
2355  clock_div_16 = 16,
2356  clock_div_32 = 32,
2357  clock_div_64 = 64,
2358  clock_div_128 = 128
2359 } clock_div_t;
2360 \endcode
2361 Clock prescaler setting enumerations for device using
2362 XTAL Divide Control Register.
2363 
2364 */
2365 typedef enum
2366 {
2367  clock_div_1 = 0,
2368  clock_div_2 = 1,
2369  clock_div_4 = 2,
2370  clock_div_8 = 3,
2371  clock_div_16 = 4,
2372  clock_div_32 = 5,
2373  clock_div_64 = 6,
2374  clock_div_128 = 7,
2375  clock_div_256 = 8
2376 #if defined(__AVR_ATmega128RFA1__) \
2377 || defined(__AVR_ATmega2564RFR2__) \
2378 || defined(__AVR_ATmega1284RFR2__) \
2379 || defined(__AVR_ATmega644RFR2__) \
2380 || defined(__AVR_ATmega256RFR2__) \
2381 || defined(__AVR_ATmega128RFR2__) \
2382 || defined(__AVR_ATmega64RFR2__)
2383  , clock_div_1_rc = 15
2384 #endif
2385 } clock_div_t;
2386 
2387 
2388 static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
2389 
2390 /** \addtogroup avr_power
2391 \code clock_prescale_set(x) \endcode
2392 
2393 Set the clock prescaler register select bits, selecting a system clock
2394 division setting. This function is inlined, even if compiler
2395 optimizations are disabled.
2396 
2397 The type of \c x is \c clock_div_t.
2398 
2399 \note For device with XTAL Divide Control Register (XDIV), \c x can actually range
2400 from 1 to 129. Thus, one does not need to use \c clock_div_t type as argument.
2401 */
2402 void clock_prescale_set(clock_div_t __x)
2403 {
2404  uint8_t __tmp = _BV(CLKPCE);
2405  __asm__ __volatile__ (
2406  "in __tmp_reg__,__SREG__" "\n\t"
2407  "cli" "\n\t"
2408  "sts %1, %0" "\n\t"
2409  "sts %1, %2" "\n\t"
2410  "out __SREG__, __tmp_reg__"
2411  : /* no outputs */
2412  : "d" (__tmp),
2413  "M" (_SFR_MEM_ADDR(CLKPR)),
2414  "d" (__x)
2415  : "r0");
2416 }
2417 
2418 /** \addtogroup avr_power
2419 \code clock_prescale_get() \endcode
2420 Gets and returns the clock prescaler register setting. The return type is \c clock_div_t.
2421 
2422 \note For device with XTAL Divide Control Register (XDIV), return can actually
2423 range from 1 to 129. Care should be taken has the return value could differ from the
2424 typedef enum clock_div_t. This should only happen if clock_prescale_set was previously
2425 called with a value other than those defined by \c clock_div_t.
2426 */
2427 #define clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
2428 
2429 #elif defined(__AVR_ATmega16HVB__) \
2430 || defined(__AVR_ATmega16HVBREVB__) \
2431 || defined(__AVR_ATmega32HVB__) \
2432 || defined(__AVR_ATmega32HVBREVB__)
2433 
2434 typedef enum
2435 {
2436  clock_div_1 = 0,
2437  clock_div_2 = 1,
2438  clock_div_4 = 2,
2439  clock_div_8 = 3
2440 } clock_div_t;
2441 
2442 static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
2443 
2444 void clock_prescale_set(clock_div_t __x)
2445 {
2446  uint8_t __tmp = _BV(CLKPCE);
2447  __asm__ __volatile__ (
2448  "in __tmp_reg__,__SREG__" "\n\t"
2449  "cli" "\n\t"
2450  "sts %1, %0" "\n\t"
2451  "sts %1, %2" "\n\t"
2452  "out __SREG__, __tmp_reg__"
2453  : /* no outputs */
2454  : "d" (__tmp),
2455  "M" (_SFR_MEM_ADDR(CLKPR)),
2456  "d" (__x)
2457  : "r0");
2458 }
2459 
2460 #define clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)))
2461 
2462 #elif defined(__AVR_ATA5790__) \
2463 || defined (__AVR_ATA5795__)
2464 
2465 typedef enum
2466 {
2467  clock_div_1 = 0,
2468  clock_div_2 = 1,
2469  clock_div_4 = 2,
2470  clock_div_8 = 3,
2471  clock_div_16 = 4,
2472  clock_div_32 = 5,
2473  clock_div_64 = 6,
2474  clock_div_128 = 7,
2475 } clock_div_t;
2476 
2477 static __inline__ void system_clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
2478 
2479 void system_clock_prescale_set(clock_div_t __x)
2480 {
2481  uint8_t __tmp = _BV(CLKPCE);
2482  __asm__ __volatile__ (
2483  "in __tmp_reg__,__SREG__" "\n\t"
2484  "cli" "\n\t"
2485  "out %1, %0" "\n\t"
2486  "out %1, %2" "\n\t"
2487  "out __SREG__, __tmp_reg__"
2488  : /* no outputs */
2489  : "d" (__tmp),
2490  "I" (_SFR_IO_ADDR(CLKPR)),
2491  "d" (__x)
2492  : "r0");
2493 }
2494 
2495 #define system_clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)))
2496 
2497 typedef enum
2498 {
2499  timer_clock_div_reset = 0,
2500  timer_clock_div_1 = 1,
2501  timer_clock_div_2 = 2,
2502  timer_clock_div_4 = 3,
2503  timer_clock_div_8 = 4,
2504  timer_clock_div_16 = 5,
2505  timer_clock_div_32 = 6,
2506  timer_clock_div_64 = 7
2507 } timer_clock_div_t;
2508 
2509 static __inline__ void timer_clock_prescale_set(timer_clock_div_t) __attribute__((__always_inline__));
2510 
2511 void timer_clock_prescale_set(timer_clock_div_t __x)
2512 {
2513  uint8_t __t;
2514  __asm__ __volatile__ (
2515  "in __tmp_reg__,__SREG__" "\n\t"
2516  "cli" "\n\t"
2517  "in %[temp],%[clkpr]" "\n\t"
2518  "out %[clkpr],%[enable]" "\n\t"
2519  "andi %[temp],%[not_CLTPS]" "\n\t"
2520  "or %[temp], %[set_value]" "\n\t"
2521  "out %[clkpr],%[temp]" "\n\t"
2522  "sei" "\n\t"
2523  "out __SREG__,__tmp_reg__" "\n\t"
2524  : /* no outputs */
2525  : [temp] "r" (__t),
2526  [clkpr] "I" (_SFR_IO_ADDR(CLKPR)),
2527  [enable] "r" (_BV(CLKPCE)),
2528  [not_CLTPS] "M" (0xFF & (~ ((1 << CLTPS2) | (1 << CLTPS1) | (1 << CLTPS0)))),
2529  [set_value] "r" ((__x & 7) << 3)
2530  : "r0");
2531 }
2532 
2533 #define timer_clock_prescale_get() (timer_clock_div_t)(CLKPR & (uint8_t)((1<<CLTPS0)|(1<<CLTPS1)|(1<<CLTPS2)))
2534 
2535 #elif defined(__AVR_ATA6285__) \
2536 || defined(__AVR_ATA6286__)
2537 
2538 typedef enum
2539 {
2540  clock_div_1 = 0,
2541  clock_div_2 = 1,
2542  clock_div_4 = 2,
2543  clock_div_8 = 3,
2544  clock_div_16 = 4,
2545  clock_div_32 = 5,
2546  clock_div_64 = 6,
2547  clock_div_128 = 7
2548 } clock_div_t;
2549 
2550 static __inline__ void system_clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
2551 
2552 void system_clock_prescale_set(clock_div_t __x)
2553 {
2554  uint8_t __t;
2555  __asm__ __volatile__ (
2556  "in __tmp_reg__,__SREG__" "\n\t"
2557  "cli" "\n\t"
2558  "in %[temp],%[clpr]" "\n\t"
2559  "out %[clpr],%[enable]" "\n\t"
2560  "andi %[temp],%[not_CLKPS]" "\n\t"
2561  "or %[temp], %[set_value]" "\n\t"
2562  "out %[clpr],%[temp]" "\n\t"
2563  "sei" "\n\t"
2564  "out __SREG__,__tmp_reg__" "\n\t"
2565  : /* no outputs */
2566  : [temp] "r" (__t),
2567  [clpr] "I" (_SFR_IO_ADDR(CLKPR)),
2568  [enable] "r" _BV(CLPCE),
2569  [not_CLKPS] "M" (0xFF & (~ ((1 << CLKPS2) | (1 << CLKPS1) | (1 << CLKPS0)))),
2570  [set_value] "r" (__x & 7)
2571  : "r0");
2572 }
2573 
2574 #define system_clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)))
2575 
2576 typedef enum
2577 {
2578  timer_clock_div_reset = 0,
2579  timer_clock_div_1 = 1,
2580  timer_clock_div_2 = 2,
2581  timer_clock_div_4 = 3,
2582  timer_clock_div_8 = 4,
2583  timer_clock_div_16 = 5,
2584  timer_clock_div_32 = 6,
2585  timer_clock_div_64 = 7
2586 } timer_clock_div_t;
2587 
2588 static __inline__ void timer_clock_prescale_set(timer_clock_div_t) __attribute__((__always_inline__));
2589 
2590 void timer_clock_prescale_set(timer_clock_div_t __x)
2591 {
2592  uint8_t __t;
2593  __asm__ __volatile__ (
2594  "in __tmp_reg__,__SREG__" "\n\t"
2595  "cli" "\n\t"
2596  "in %[temp],%[clpr]" "\n\t"
2597  "out %[clpr],%[enable]" "\n\t"
2598  "andi %[temp],%[not_CLTPS]" "\n\t"
2599  "or %[temp], %[set_value]" "\n\t"
2600  "out %[clpr],%[temp]" "\n\t"
2601  "sei" "\n\t"
2602  "out __SREG__,__tmp_reg__" "\n\t"
2603  : /* no outputs */
2604  : [temp] "r" (__t),
2605  [clpr] "I" (_SFR_IO_ADDR(CLKPR)),
2606  [enable] "r" (_BV(CLPCE)),
2607  [not_CLTPS] "M" (0xFF & (~ ((1 << CLTPS2) | (1 << CLTPS1) | (1 << CLTPS0)))),
2608  [set_value] "r" ((__x & 7) << 3)
2609  : "r0");
2610 }
2611 
2612 #define timer_clock_prescale_get() (timer_clock_div_t)(CLKPR & (uint8_t)((1<<CLTPS0)|(1<<CLTPS1)|(1<<CLTPS2)))
2613 
2614 #elif defined(__AVR_ATtiny24__) \
2615 || defined(__AVR_ATtiny24A__) \
2616 || defined(__AVR_ATtiny44__) \
2617 || defined(__AVR_ATtiny44A__) \
2618 || defined(__AVR_ATtiny84__) \
2619 || defined(__AVR_ATtiny84A__) \
2620 || defined(__AVR_ATtiny25__) \
2621 || defined(__AVR_ATtiny45__) \
2622 || defined(__AVR_ATtiny85__) \
2623 || defined(__AVR_ATtiny261A__) \
2624 || defined(__AVR_ATtiny261__) \
2625 || defined(__AVR_ATtiny461__) \
2626 || defined(__AVR_ATtiny461A__) \
2627 || defined(__AVR_ATtiny861__) \
2628 || defined(__AVR_ATtiny861A__) \
2629 || defined(__AVR_ATtiny2313__) \
2630 || defined(__AVR_ATtiny2313A__) \
2631 || defined(__AVR_ATtiny4313__) \
2632 || defined(__AVR_ATtiny13__) \
2633 || defined(__AVR_ATtiny13A__) \
2634 || defined(__AVR_ATtiny43U__) \
2635 
2636 typedef enum
2637 {
2638  clock_div_1 = 0,
2639  clock_div_2 = 1,
2640  clock_div_4 = 2,
2641  clock_div_8 = 3,
2642  clock_div_16 = 4,
2643  clock_div_32 = 5,
2644  clock_div_64 = 6,
2645  clock_div_128 = 7,
2646  clock_div_256 = 8
2647 } clock_div_t;
2648 
2649 static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
2650 
2651 void clock_prescale_set(clock_div_t __x)
2652 {
2653  uint8_t __tmp = _BV(CLKPCE);
2654  __asm__ __volatile__ (
2655  "in __tmp_reg__,__SREG__" "\n\t"
2656  "cli" "\n\t"
2657  "out %1, %0" "\n\t"
2658  "out %1, %2" "\n\t"
2659  "out __SREG__, __tmp_reg__"
2660  : /* no outputs */
2661  : "d" (__tmp),
2662  "I" (_SFR_IO_ADDR(CLKPR)),
2663  "d" (__x)
2664  : "r0");
2665 }
2666 
2667 
2668 #define clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
2669 
2670 #elif defined(__AVR_ATmega64__) \
2671 || defined(__AVR_ATmega103__) \
2672 || defined(__AVR_ATmega128__)
2673 
2674 //Enum is declared for code compatibility
2675 typedef enum
2676 {
2677  clock_div_1 = 1,
2678  clock_div_2 = 2,
2679  clock_div_4 = 4,
2680  clock_div_8 = 8,
2681  clock_div_16 = 16,
2682  clock_div_32 = 32,
2683  clock_div_64 = 64,
2684  clock_div_128 = 128
2685 } clock_div_t;
2686 
2687 static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
2688 
2689 void clock_prescale_set(clock_div_t __x)
2690 {
2691  if((__x <= 0) || (__x > 129))
2692  {
2693  return;//Invalid value.
2694  }
2695  else
2696  {
2697  uint8_t __tmp = 0;
2698  //Algo explained:
2699  //1 - Clear XDIV in order for it to accept a new value (actually only
2700  // XDIVEN need to be cleared, but clearing XDIV is faster than
2701  // read-modify-write since we will rewrite XDIV later anyway)
2702  //2 - wait 8 clock cycle for stability, see datasheet erreta
2703  //3 - Exist if requested prescaller is 1
2704  //4 - Calculate XDIV6..0 value = 129 - __x
2705  //5 - Set XDIVEN bit in calculated value
2706  //6 - write XDIV with calculated value
2707  //7 - wait 8 clock cycle for stability, see datasheet erreta
2708  __asm__ __volatile__ (
2709  "in __tmp_reg__,__SREG__" "\n\t"
2710  "cli" "\n\t"
2711  "out %1, __zero_reg__" "\n\t"
2712  "nop" "\n\t"
2713  "nop" "\n\t"
2714  "nop" "\n\t"
2715  "nop" "\n\t"
2716  "nop" "\n\t"
2717  "nop" "\n\t"
2718  "nop" "\n\t"
2719  "nop" "\n\t"
2720  "cpi %0, 0x01" "\n\t"
2721  "breq L_%=" "\n\t"
2722  "ldi %2, 0x81" "\n\t" //129
2723  "sub %2, %0" "\n\t"
2724  "ori %2, 0x80" "\n\t" //128
2725  "out %1, %2" "\n\t"
2726  "nop" "\n\t"
2727  "nop" "\n\t"
2728  "nop" "\n\t"
2729  "nop" "\n\t"
2730  "nop" "\n\t"
2731  "nop" "\n\t"
2732  "nop" "\n\t"
2733  "nop" "\n\t"
2734  "L_%=: " "out __SREG__, __tmp_reg__"
2735  : /* no outputs */
2736  :"d" (__x),
2737  "I" (_SFR_IO_ADDR(XDIV)),
2738  "d" (__tmp)
2739  : "r0");
2740  }
2741 }
2742 
2743 static __inline__ clock_div_t clock_prescale_get(void) __attribute__((__always_inline__));
2744 
2745 clock_div_t clock_prescale_get(void)
2746 {
2747  if(bit_is_clear(XDIV, XDIVEN))
2748  {
2749  return 1;
2750  }
2751  else
2752  {
2753  return (clock_div_t)(129 - (XDIV & 0x7F));
2754  }
2755 }
2756 
2757 #elif defined(__AVR_ATtiny4__) \
2758 || defined(__AVR_ATtiny5__) \
2759 || defined(__AVR_ATtiny9__) \
2760 || defined(__AVR_ATtiny10__) \
2761 || defined(__AVR_ATtiny20__) \
2762 || defined(__AVR_ATtiny40__) \
2763 
2764 typedef enum
2765 {
2766  clock_div_1 = 0,
2767  clock_div_2 = 1,
2768  clock_div_4 = 2,
2769  clock_div_8 = 3,
2770  clock_div_16 = 4,
2771  clock_div_32 = 5,
2772  clock_div_64 = 6,
2773  clock_div_128 = 7,
2774  clock_div_256 = 8
2775 } clock_div_t;
2776 
2777 static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
2778 
2779 void clock_prescale_set(clock_div_t __x)
2780 {
2781  uint8_t __tmp = 0xD8;
2782  __asm__ __volatile__ (
2783  "in __tmp_reg__,__SREG__" "\n\t"
2784  "cli" "\n\t"
2785  "out %1, %0" "\n\t"
2786  "out %2, %3" "\n\t"
2787  "out __SREG__, __tmp_reg__"
2788  : /* no outputs */
2789  : "d" (__tmp),
2790  "I" (_SFR_IO_ADDR(CCP)),
2791  "I" (_SFR_IO_ADDR(CLKPSR)),
2792  "d" (__x)
2793  : "r16");
2794 }
2795 
2796 #define clock_prescale_get() (clock_div_t)(CLKPSR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
2797 
2798 #endif
2799 
2800 #endif /* _AVR_POWER_H_ */
bit_is_clear
#define bit_is_clear(sfr, bit)
Definition: sfr_defs.h:245
uint8_t
unsigned char uint8_t
Definition: stdint.h:80
_BV
#define _BV(bit)
Definition: sfr_defs.h:208

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