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sleep.h
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1 /* Copyright (c) 2002, 2004 Theodore A. Roth
2  Copyright (c) 2004, 2007, 2008 Eric B. Weddington
3  Copyright (c) 2005, 2006, 2007 Joerg Wunsch
4  All rights reserved.
5 
6  Redistribution and use in source and binary forms, with or without
7  modification, are permitted provided that the following conditions are met:
8 
9  * Redistributions of source code must retain the above copyright
10  notice, this list of conditions and the following disclaimer.
11 
12  * Redistributions in binary form must reproduce the above copyright
13  notice, this list of conditions and the following disclaimer in
14  the documentation and/or other materials provided with the
15  distribution.
16 
17  * Neither the name of the copyright holders nor the names of
18  contributors may be used to endorse or promote products derived
19  from this software without specific prior written permission.
20 
21  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  POSSIBILITY OF SUCH DAMAGE. */
32 
33 /* $Id: sleep.h 2433 2014-07-30 10:58:44Z pitchumani $ */
34 
35 #ifndef _AVR_SLEEP_H_
36 #define _AVR_SLEEP_H_ 1
37 
38 #include <avr/io.h>
39 #include <stdint.h>
40 
41 
42 /** \file */
43 
44 /** \defgroup avr_sleep <avr/sleep.h>: Power Management and Sleep Modes
45 
46  \code #include <avr/sleep.h>\endcode
47 
48  Use of the \c SLEEP instruction can allow an application to reduce its
49  power comsumption considerably. AVR devices can be put into different
50  sleep modes. Refer to the datasheet for the details relating to the device
51  you are using.
52 
53  There are several macros provided in this header file to actually
54  put the device into sleep mode. The simplest way is to optionally
55  set the desired sleep mode using \c set_sleep_mode() (it usually
56  defaults to idle mode where the CPU is put on sleep but all
57  peripheral clocks are still running), and then call
58  \c sleep_mode(). This macro automatically sets the sleep enable bit, goes
59  to sleep, and clears the sleep enable bit.
60 
61  Example:
62  \code
63  #include <avr/sleep.h>
64 
65  ...
66  set_sleep_mode(<mode>);
67  sleep_mode();
68  \endcode
69 
70  Note that unless your purpose is to completely lock the CPU (until a
71  hardware reset), interrupts need to be enabled before going to sleep.
72 
73  As the \c sleep_mode() macro might cause race conditions in some
74  situations, the individual steps of manipulating the sleep enable
75  (SE) bit, and actually issuing the \c SLEEP instruction, are provided
76  in the macros \c sleep_enable(), \c sleep_disable(), and
77  \c sleep_cpu(). This also allows for test-and-sleep scenarios that
78  take care of not missing the interrupt that will awake the device
79  from sleep.
80 
81  Example:
82  \code
83  #include <avr/interrupt.h>
84  #include <avr/sleep.h>
85 
86  ...
87  set_sleep_mode(<mode>);
88  cli();
89  if (some_condition)
90  {
91  sleep_enable();
92  sei();
93  sleep_cpu();
94  sleep_disable();
95  }
96  sei();
97  \endcode
98 
99  This sequence ensures an atomic test of \c some_condition with
100  interrupts being disabled. If the condition is met, sleep mode
101  will be prepared, and the \c SLEEP instruction will be scheduled
102  immediately after an \c SEI instruction. As the intruction right
103  after the \c SEI is guaranteed to be executed before an interrupt
104  could trigger, it is sure the device will really be put to sleep.
105 
106  Some devices have the ability to disable the Brown Out Detector (BOD) before
107  going to sleep. This will also reduce power while sleeping. If the
108  specific AVR device has this ability then an additional macro is defined:
109  \c sleep_bod_disable(). This macro generates inlined assembly code
110  that will correctly implement the timed sequence for disabling the BOD
111  before sleeping. However, there is a limited number of cycles after the
112  BOD has been disabled that the device can be put into sleep mode, otherwise
113  the BOD will not truly be disabled. Recommended practice is to disable
114  the BOD (\c sleep_bod_disable()), set the interrupts (\c sei()), and then
115  put the device to sleep (\c sleep_cpu()), like so:
116 
117  \code
118  #include <avr/interrupt.h>
119  #include <avr/sleep.h>
120 
121  ...
122  set_sleep_mode(<mode>);
123  cli();
124  if (some_condition)
125  {
126  sleep_enable();
127  sleep_bod_disable();
128  sei();
129  sleep_cpu();
130  sleep_disable();
131  }
132  sei();
133  \endcode
134 */
135 
136 
137 /* Define an internal sleep control register and an internal sleep enable bit mask. */
138 #if defined(SLEEP_CTRL)
139 
140  /* XMEGA devices */
141  #define _SLEEP_CONTROL_REG SLEEP_CTRL
142  #define _SLEEP_ENABLE_MASK SLEEP_SEN_bm
143 
144 #elif defined(SMCR)
145 
146  #define _SLEEP_CONTROL_REG SMCR
147  #define _SLEEP_ENABLE_MASK _BV(SE)
148 
149 #elif defined(__AVR_AT94K__)
150 
151  #define _SLEEP_CONTROL_REG MCUR
152  #define _SLEEP_ENABLE_MASK _BV(SE)
153 
154 #else
155 
156  #define _SLEEP_CONTROL_REG MCUCR
157  #define _SLEEP_ENABLE_MASK _BV(SE)
158 
159 #endif
160 
161 
162 /* Define set_sleep_mode() and sleep mode values per device. */
163 #if defined(__AVR_ATmega161__)
164 
165  #define SLEEP_MODE_IDLE 0
166  #define SLEEP_MODE_PWR_DOWN 1
167  #define SLEEP_MODE_PWR_SAVE 2
168 
169  #define set_sleep_mode(mode) \
170  do { \
171  MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_PWR_DOWN || (mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM1) : 0)); \
172  EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM0) : 0)); \
173  } while(0)
174 
175 
176 #elif defined(__AVR_ATmega162__) \
177 || defined(__AVR_ATmega8515__)
178 
179  #define SLEEP_MODE_IDLE 0
180  #define SLEEP_MODE_PWR_DOWN 1
181  #define SLEEP_MODE_PWR_SAVE 2
182  #define SLEEP_MODE_ADC 3
183  #define SLEEP_MODE_STANDBY 4
184  #define SLEEP_MODE_EXT_STANDBY 5
185 
186  #define set_sleep_mode(mode) \
187  do { \
188  MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_IDLE ? 0 : _BV(SM1))); \
189  MCUCSR = ((MCUCSR & ~_BV(SM2)) | ((mode) == SLEEP_MODE_STANDBY || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM2) : 0)); \
190  EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM0) : 0)); \
191  } while(0)
192 
193 #elif defined(__AVR_AT90S2313__) \
194 || defined(__AVR_AT90S2323__) \
195 || defined(__AVR_AT90S2333__) \
196 || defined(__AVR_AT90S2343__) \
197 || defined(__AVR_AT43USB320__) \
198 || defined(__AVR_AT43USB355__) \
199 || defined(__AVR_AT90S4414__) \
200 || defined(__AVR_AT90S4433__) \
201 || defined(__AVR_AT90S8515__) \
202 || defined(__AVR_ATtiny22__)
203 
204  #define SLEEP_MODE_IDLE 0
205  #define SLEEP_MODE_PWR_DOWN _BV(SM)
206 
207  #define set_sleep_mode(mode) \
208  do { \
209  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~_BV(SM)) | (mode)); \
210  } while(0)
211 
212 #elif defined(__AVR_ATtiny167__) \
213 || defined(__AVR_ATtiny87__) \
214 || defined(__AVR_ATtiny828__)
215 
216  #define SLEEP_MODE_IDLE 0
217  #define SLEEP_MODE_ADC _BV(SM0)
218  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
219 
220  #define set_sleep_mode(mode) \
221  do { \
222  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
223  } while(0)
224 
225 #elif defined(__AVR_AT90S4434__) \
226 || defined(__AVR_ATA5505__) \
227 || defined(__AVR_ATA5272__) \
228 || defined(__AVR_AT76C711__) \
229 || defined(__AVR_AT90S8535__) \
230 || defined(__AVR_ATmega103__) \
231 || defined(__AVR_ATmega161__) \
232 || defined(__AVR_ATmega163__) \
233 || defined(__AVR_ATmega16HVB__) \
234 || defined(__AVR_ATmega16HVBREVB__) \
235 || defined(__AVR_ATmega32HVB__) \
236 || defined(__AVR_ATmega32HVBREVB__) \
237 || defined(__AVR_ATtiny13__) \
238 || defined(__AVR_ATtiny13A__) \
239 || defined(__AVR_ATtiny15__) \
240 || defined(__AVR_ATtiny24__) \
241 || defined(__AVR_ATtiny24A__) \
242 || defined(__AVR_ATtiny44__) \
243 || defined(__AVR_ATtiny44A__) \
244 || defined(__AVR_ATtiny84__) \
245 || defined(__AVR_ATtiny84A__) \
246 || defined(__AVR_ATtiny25__) \
247 || defined(__AVR_ATtiny45__) \
248 || defined(__AVR_ATtiny48__) \
249 || defined(__AVR_ATtiny85__) \
250 || defined(__AVR_ATtiny88__)
251 
252  #define SLEEP_MODE_IDLE 0
253  #define SLEEP_MODE_ADC _BV(SM0)
254  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
255  #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
256 
257  #define set_sleep_mode(mode) \
258  do { \
259  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
260  } while(0)
261 
262 #elif defined(__AVR_ATtiny2313__) \
263 || defined(__AVR_ATtiny2313A__) \
264 || defined(__AVR_ATtiny4313__)
265 
266  #define SLEEP_MODE_IDLE 0
267  #define SLEEP_MODE_PWR_DOWN (_BV(SM0) | _BV(SM1))
268  #define SLEEP_MODE_STANDBY _BV(SM1)
269 
270  #define set_sleep_mode(mode) \
271  do { \
272  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
273  } while(0)
274 
275 #elif defined(__AVR_AT94K__)
276 
277  #define SLEEP_MODE_IDLE 0
278  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
279  #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
280 
281  #define set_sleep_mode(mode) \
282  do { \
283  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
284  } while(0)
285 
286 #elif defined(__AVR_ATtiny26__) \
287 || defined(__AVR_ATtiny261__) \
288 || defined(__AVR_ATtiny261A__) \
289 || defined(__AVR_ATtiny461__) \
290 || defined(__AVR_ATtiny461A__) \
291 || defined(__AVR_ATtiny861__) \
292 || defined(__AVR_ATtiny861A__) \
293 || defined(__AVR_ATtiny43U__) \
294 || defined(__AVR_ATtiny1634__)
295 
296  #define SLEEP_MODE_IDLE 0
297  #define SLEEP_MODE_ADC _BV(SM0)
298  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
299  #define SLEEP_MODE_STANDBY (_BV(SM0) | _BV(SM1))
300 
301  #define set_sleep_mode(mode) \
302  do { \
303  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
304  } while(0)
305 
306 #elif defined(__AVR_AT90PWM216__) \
307 || defined(__AVR_AT90PWM316__) \
308 || defined(__AVR_AT90PWM161__) \
309 || defined(__AVR_AT90PWM81__)
310 
311  #define SLEEP_MODE_IDLE 0
312  #define SLEEP_MODE_ADC _BV(SM0)
313  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
314  #define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2))
315 
316  #define set_sleep_mode(mode) \
317  do { \
318  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
319  } while(0)
320 
321 #elif defined(__AVR_AT90CAN128__) \
322 || defined(__AVR_AT90CAN32__) \
323 || defined(__AVR_AT90CAN64__) \
324 || defined(__AVR_AT90PWM1__) \
325 || defined(__AVR_AT90PWM2__) \
326 || defined(__AVR_AT90PWM2B__) \
327 || defined(__AVR_AT90PWM3__) \
328 || defined(__AVR_AT90PWM3B__) \
329 || defined(__AVR_AT90USB162__) \
330 || defined(__AVR_AT90USB82__) \
331 || defined(__AVR_AT90USB1286__) \
332 || defined(__AVR_AT90USB1287__) \
333 || defined(__AVR_AT90USB646__) \
334 || defined(__AVR_AT90USB647__) \
335 || defined(__AVR_ATmega128__) \
336 || defined(__AVR_ATmega128A__) \
337 || defined(__AVR_ATmega1280__) \
338 || defined(__AVR_ATmega1281__) \
339 || defined(__AVR_ATmega1284__) \
340 || defined(__AVR_ATmega1284P__) \
341 || defined(__AVR_ATmega128RFA1__) \
342 || defined(__AVR_ATmega1284RFR2__) \
343 || defined(__AVR_ATmega128RFR2__) \
344 || defined(__AVR_ATmega16__) \
345 || defined(__AVR_ATmega16A__) \
346 || defined(__AVR_ATmega162__) \
347 || defined(__AVR_ATmega164A__) \
348 || defined(__AVR_ATmega164P__) \
349 || defined(__AVR_ATmega164PA__) \
350 || defined(__AVR_ATmega165__) \
351 || defined(__AVR_ATmega165A__) \
352 || defined(__AVR_ATmega165P__) \
353 || defined(__AVR_ATmega165PA__) \
354 || defined(__AVR_ATmega168__) \
355 || defined(__AVR_ATmega168A__) \
356 || defined(__AVR_ATmega168P__) \
357 || defined(__AVR_ATmega168PA__) \
358 || defined(__AVR_ATmega169__) \
359 || defined(__AVR_ATmega169A__) \
360 || defined(__AVR_ATmega169P__) \
361 || defined(__AVR_ATmega169PA__) \
362 || defined(__AVR_ATmega16HVA__) \
363 || defined(__AVR_ATmega16HVA2__) \
364 || defined(__AVR_ATmega16M1__) \
365 || defined(__AVR_ATmega16U2__) \
366 || defined(__AVR_ATmega16U4__) \
367 || defined(__AVR_ATmega2560__) \
368 || defined(__AVR_ATmega2561__) \
369 || defined(__AVR_ATmega2564RFR2__) \
370 || defined(__AVR_ATmega256RFR2__) \
371 || defined(__AVR_ATmega32__) \
372 || defined(__AVR_ATmega32A__) \
373 || defined(__AVR_ATmega323__) \
374 || defined(__AVR_ATmega324A__) \
375 || defined(__AVR_ATmega324P__) \
376 || defined(__AVR_ATmega324PA__) \
377 || defined(__AVR_ATmega325__) \
378 || defined(__AVR_ATmega325A__) \
379 || defined(__AVR_ATmega325PA__) \
380 || defined(__AVR_ATmega3250__) \
381 || defined(__AVR_ATmega3250A__) \
382 || defined(__AVR_ATmega3250PA__) \
383 || defined(__AVR_ATmega328__) \
384 || defined(__AVR_ATmega328P__) \
385 || defined(__AVR_ATmega329__) \
386 || defined(__AVR_ATmega329A__) \
387 || defined(__AVR_ATmega329P__) \
388 || defined(__AVR_ATmega329PA__) \
389 || defined(__AVR_ATmega3290__) \
390 || defined(__AVR_ATmega3290A__) \
391 || defined(__AVR_ATmega3290P__) \
392 || defined(__AVR_ATmega3290PA__) \
393 || defined(__AVR_ATmega32C1__) \
394 || defined(__AVR_ATmega32M1__) \
395 || defined(__AVR_ATmega32U2__) \
396 || defined(__AVR_ATmega32U4__) \
397 || defined(__AVR_ATmega32U6__) \
398 || defined(__AVR_ATmega406__) \
399 || defined(__AVR_ATmega48__) \
400 || defined(__AVR_ATmega48A__) \
401 || defined(__AVR_ATmega48PA__) \
402 || defined(__AVR_ATmega48P__) \
403 || defined(__AVR_ATmega64__) \
404 || defined(__AVR_ATmega64A__) \
405 || defined(__AVR_ATmega640__) \
406 || defined(__AVR_ATmega644__) \
407 || defined(__AVR_ATmega644A__) \
408 || defined(__AVR_ATmega644P__) \
409 || defined(__AVR_ATmega644PA__) \
410 || defined(__AVR_ATmega645__) \
411 || defined(__AVR_ATmega645A__) \
412 || defined(__AVR_ATmega645P__) \
413 || defined(__AVR_ATmega6450__) \
414 || defined(__AVR_ATmega6450A__) \
415 || defined(__AVR_ATmega6450P__) \
416 || defined(__AVR_ATmega649__) \
417 || defined(__AVR_ATmega649A__) \
418 || defined(__AVR_ATmega6490__) \
419 || defined(__AVR_ATmega6490A__) \
420 || defined(__AVR_ATmega6490P__) \
421 || defined(__AVR_ATmega649P__) \
422 || defined(__AVR_ATmega64C1__) \
423 || defined(__AVR_ATmega64HVE__) \
424 || defined(__AVR_ATmega64M1__) \
425 || defined(__AVR_ATmega644RFR2__) \
426 || defined(__AVR_ATmega64RFR2__) \
427 || defined(__AVR_ATmega8__) \
428 || defined(__AVR_ATmega8A__) \
429 || defined(__AVR_ATmega8515__) \
430 || defined(__AVR_ATmega8535__) \
431 || defined(__AVR_ATmega88__) \
432 || defined(__AVR_ATmega88A__) \
433 || defined(__AVR_ATmega88P__) \
434 || defined(__AVR_ATmega88PA__) \
435 || defined(__AVR_ATmega8HVA__) \
436 || defined(__AVR_ATmega8U2__)
437 
438 
439  #define SLEEP_MODE_IDLE (0)
440  #define SLEEP_MODE_ADC _BV(SM0)
441  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
442  #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
443  #define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2))
444  #define SLEEP_MODE_EXT_STANDBY (_BV(SM0) | _BV(SM1) | _BV(SM2))
445 
446 
447  #define set_sleep_mode(mode) \
448  do { \
449  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
450  } while(0)
451 
452 #elif defined(__AVR_ATxmega16A4__) \
453 || defined(__AVR_ATxmega16A4U__) \
454 || defined(__AVR_ATxmega16C4__) \
455 || defined(__AVR_ATxmega16D4__) \
456 || defined(__AVR_ATxmega32A4__) \
457 || defined(__AVR_ATxmega32A4U__) \
458 || defined(__AVR_ATxmega32C4__) \
459 || defined(__AVR_ATxmega32D4__) \
460 || defined(__AVR_ATxmega64A1__) \
461 || defined(__AVR_ATxmega64A1U__) \
462 || defined(__AVR_ATxmega64A3__) \
463 || defined(__AVR_ATxmega64A3U__) \
464 || defined(__AVR_ATxmega64A4U__) \
465 || defined(__AVR_ATxmega64B1__) \
466 || defined(__AVR_ATxmega64B3__) \
467 || defined(__AVR_ATxmega64C3__) \
468 || defined(__AVR_ATxmega64D3__) \
469 || defined(__AVR_ATxmega64D4__) \
470 || defined(__AVR_ATxmega128A1__) \
471 || defined(__AVR_ATxmega128A1U__) \
472 || defined(__AVR_ATxmega128A3__) \
473 || defined(__AVR_ATxmega128A3U__) \
474 || defined(__AVR_ATxmega128A4U__) \
475 || defined(__AVR_ATxmega128B1__) \
476 || defined(__AVR_ATxmega128B3__) \
477 || defined(__AVR_ATxmega128C3__) \
478 || defined(__AVR_ATxmega128D3__) \
479 || defined(__AVR_ATxmega128D4__) \
480 || defined(__AVR_ATxmega192A3__) \
481 || defined(__AVR_ATxmega192A3U__) \
482 || defined(__AVR_ATxmega192C3__) \
483 || defined(__AVR_ATxmega192D3__) \
484 || defined(__AVR_ATxmega256A3__) \
485 || defined(__AVR_ATxmega256A3U__) \
486 || defined(__AVR_ATxmega256C3__) \
487 || defined(__AVR_ATxmega256D3__) \
488 || defined(__AVR_ATxmega256A3B__) \
489 || defined(__AVR_ATxmega256A3BU__) \
490 || defined(__AVR_ATxmega384C3__) \
491 || defined(__AVR_ATxmega384D3__)
492 
493  #define SLEEP_MODE_IDLE (0)
494  #define SLEEP_MODE_PWR_DOWN (SLEEP_SMODE1_bm)
495  #define SLEEP_MODE_PWR_SAVE (SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)
496  #define SLEEP_MODE_STANDBY (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm)
497  #define SLEEP_MODE_EXT_STANDBY (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)
498 
499  #define set_sleep_mode(mode) \
500  do { \
501  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)) | (mode)); \
502  } while(0)
503 
504 #elif defined(__AVR_AT90SCR100__)
505 
506  #define SLEEP_MODE_IDLE (0)
507  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
508  #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
509  #define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2))
510  #define SLEEP_MODE_EXT_STANDBY (_BV(SM0) | _BV(SM1) | _BV(SM2))
511 
512  #define set_sleep_mode(mode) \
513  do { \
514  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
515  } while(0)
516 
517 #elif defined(__AVR_ATA6285__) \
518 || defined(__AVR_ATA6286__) \
519 || defined(__AVR_ATA6289__)
520 
521  #define SLEEP_MODE_IDLE (0)
522  #define SLEEP_MODE_SENSOR_NOISE_REDUCTION (_BV(SM0))
523  #define SLEEP_MODE_PWR_DOWN (_BV(SM1))
524 
525  #define set_sleep_mode(mode) \
526  do { \
527  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
528  } while(0)
529 
530 #elif defined (__AVR_ATA5790__) \
531 || defined (__AVR_ATA5795__)
532 
533  #define SLEEP_MODE_IDLE (0)
534  #define SLEEP_MODE_EXT_PWR_SAVE (_BV(SM0))
535  #define SLEEP_MODE_PWR_DOWN (_BV(SM1))
536  #define SLEEP_MODE_PWR_SAVE (_BV(SM1) | _BV(SM0))
537 
538  #define set_sleep_mode(mode) \
539  do { \
540  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
541  } while(0)
542 
543 #elif defined(__AVR_ATtiny4__) \
544 || defined(__AVR_ATtiny5__) \
545 || defined(__AVR_ATtiny9__) \
546 || defined(__AVR_ATtiny10__) \
547 || defined(__AVR_ATtiny20__) \
548 || defined(__AVR_ATtiny40__)
549 
550  #define SLEEP_MODE_IDLE 0
551  #define SLEEP_MODE_ADC _BV(SM0)
552  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
553  #define SLEEP_MODE_STANDBY _BV(SM2)
554 
555  #define set_sleep_mode(mode) \
556  do { \
557  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
558  } while(0)
559 
560 #else
561 
562  #error "No SLEEP mode defined for this device."
563 
564 #endif
565 
566 
567 
568 /** \ingroup avr_sleep
569 
570  Put the device in sleep mode. How the device is brought out of sleep mode
571  depends on the specific mode selected with the set_sleep_mode() function.
572  See the data sheet for your device for more details. */
573 
574 
575 #if defined(__DOXYGEN__)
576 
577 /** \ingroup avr_sleep
578 
579  Set the SE (sleep enable) bit.
580 */
581 extern void sleep_enable (void);
582 
583 #else
584 
585 #define sleep_enable() \
586 do { \
587  _SLEEP_CONTROL_REG |= (uint8_t)_SLEEP_ENABLE_MASK; \
588 } while(0)
589 
590 #endif
591 
592 
593 #if defined(__DOXYGEN__)
594 
595 /** \ingroup avr_sleep
596 
597  Clear the SE (sleep enable) bit.
598 */
599 extern void sleep_disable (void);
600 
601 #else
602 
603 #define sleep_disable() \
604 do { \
605  _SLEEP_CONTROL_REG &= (uint8_t)(~_SLEEP_ENABLE_MASK); \
606 } while(0)
607 
608 #endif
609 
610 
611 /** \ingroup avr_sleep
612 
613  Put the device into sleep mode. The SE bit must be set
614  beforehand, and it is recommended to clear it afterwards.
615 */
616 #if defined(__DOXYGEN__)
617 
618 extern void sleep_cpu (void);
619 
620 #else
621 
622 #define sleep_cpu() \
623 do { \
624  __asm__ __volatile__ ( "sleep" "\n\t" :: ); \
625 } while(0)
626 
627 #endif
628 
629 
630 #if defined(__DOXYGEN__)
631 
632 extern void sleep_mode (void);
633 
634 #else
635 
636 #define sleep_mode() \
637 do { \
638  sleep_enable(); \
639  sleep_cpu(); \
640  sleep_disable(); \
641 } while (0)
642 
643 #endif
644 
645 
646 #if defined(__DOXYGEN__)
647 
648 extern void sleep_bod_disable (void);
649 
650 #else
651 
652 #if defined(BODS) && defined(BODSE)
653 
654 #ifdef BODCR
655 
656 #define BOD_CONTROL_REG BODCR
657 
658 #else
659 
660 #define BOD_CONTROL_REG MCUCR
661 
662 #endif
663 
664 #define sleep_bod_disable() \
665 do { \
666  uint8_t tempreg; \
667  __asm__ __volatile__("in %[tempreg], %[mcucr]" "\n\t" \
668  "ori %[tempreg], %[bods_bodse]" "\n\t" \
669  "out %[mcucr], %[tempreg]" "\n\t" \
670  "andi %[tempreg], %[not_bodse]" "\n\t" \
671  "out %[mcucr], %[tempreg]" \
672  : [tempreg] "=&d" (tempreg) \
673  : [mcucr] "I" _SFR_IO_ADDR(BOD_CONTROL_REG), \
674  [bods_bodse] "i" (_BV(BODS) | _BV(BODSE)), \
675  [not_bodse] "i" (~_BV(BODSE))); \
676 } while (0)
677 
678 #endif
679 
680 #endif
681 
682 
683 /*@}*/
684 
685 #endif /* _AVR_SLEEP_H_ */
sleep_cpu
void sleep_cpu(void)
sleep_enable
void sleep_enable(void)
sleep_disable
void sleep_disable(void)

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