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wdt.h
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1 /* Copyright (c) 2002, 2004 Marek Michalkiewicz
2  Copyright (c) 2005, 2006, 2007 Eric B. Weddington
3  All rights reserved.
4 
5  Redistribution and use in source and binary forms, with or without
6  modification, are permitted provided that the following conditions are met:
7 
8  * Redistributions of source code must retain the above copyright
9  notice, this list of conditions and the following disclaimer.
10 
11  * Redistributions in binary form must reproduce the above copyright
12  notice, this list of conditions and the following disclaimer in
13  the documentation and/or other materials provided with the
14  distribution.
15 
16  * Neither the name of the copyright holders nor the names of
17  contributors may be used to endorse or promote products derived
18  from this software without specific prior written permission.
19 
20  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30  POSSIBILITY OF SUCH DAMAGE. */
31 
32 /* $Id: wdt.h 2431 2014-05-19 14:42:43Z pitchumani $ */
33 
34 /*
35  avr/wdt.h - macros for AVR watchdog timer
36  */
37 
38 #ifndef _AVR_WDT_H_
39 #define _AVR_WDT_H_
40 
41 #include <avr/io.h>
42 #include <stdint.h>
43 
44 /** \file */
45 /** \defgroup avr_watchdog <avr/wdt.h>: Watchdog timer handling
46  \code #include <avr/wdt.h> \endcode
47 
48  This header file declares the interface to some inline macros
49  handling the watchdog timer present in many AVR devices. In order
50  to prevent the watchdog timer configuration from being
51  accidentally altered by a crashing application, a special timed
52  sequence is required in order to change it. The macros within
53  this header file handle the required sequence automatically
54  before changing any value. Interrupts will be disabled during
55  the manipulation.
56 
57  \note Depending on the fuse configuration of the particular
58  device, further restrictions might apply, in particular it might
59  be disallowed to turn off the watchdog timer.
60 
61  Note that for newer devices (ATmega88 and newer, effectively any
62  AVR that has the option to also generate interrupts), the watchdog
63  timer remains active even after a system reset (except a power-on
64  condition), using the fastest prescaler value (approximately 15
65  ms). It is therefore required to turn off the watchdog early
66  during program startup, the datasheet recommends a sequence like
67  the following:
68 
69  \code
70  #include <stdint.h>
71  #include <avr/wdt.h>
72 
73  uint8_t mcusr_mirror __attribute__ ((section (".noinit")));
74 
75  void get_mcusr(void) \
76  __attribute__((naked)) \
77  __attribute__((section(".init3")));
78  void get_mcusr(void)
79  {
80  mcusr_mirror = MCUSR;
81  MCUSR = 0;
82  wdt_disable();
83  }
84  \endcode
85 
86  Saving the value of MCUSR in \c mcusr_mirror is only needed if the
87  application later wants to examine the reset source, but in particular,
88  clearing the watchdog reset flag before disabling the
89  watchdog is required, according to the datasheet.
90 */
91 
92 /**
93  \ingroup avr_watchdog
94  Reset the watchdog timer. When the watchdog timer is enabled,
95  a call to this instruction is required before the timer expires,
96  otherwise a watchdog-initiated device reset will occur.
97 */
98 
99 #define wdt_reset() __asm__ __volatile__ ("wdr")
100 
101 
102 #if defined(WDP3)
103 # define _WD_PS3_MASK _BV(WDP3)
104 #else
105 # define _WD_PS3_MASK 0x00
106 #endif
107 
108 #if defined(WDTCSR)
109 # define _WD_CONTROL_REG WDTCSR
110 #elif defined(WDTCR)
111 # define _WD_CONTROL_REG WDTCR
112 #else
113 # define _WD_CONTROL_REG WDT
114 #endif
115 
116 #if defined(WDTOE)
117 #define _WD_CHANGE_BIT WDTOE
118 #else
119 #define _WD_CHANGE_BIT WDCE
120 #endif
121 
122 
123 /**
124  \ingroup avr_watchdog
125  Enable the watchdog timer, configuring it for expiry after
126  \c timeout (which is a combination of the \c WDP0 through
127  \c WDP2 bits to write into the \c WDTCR register; For those devices
128  that have a \c WDTCSR register, it uses the combination of the \c WDP0
129  through \c WDP3 bits).
130 
131  See also the symbolic constants \c WDTO_15MS et al.
132 */
133 
134 
135 #if defined(__AVR_ATxmega16A4__) \
136 || defined(__AVR_ATxmega16A4U__) \
137 || defined(__AVR_ATxmega16C4__) \
138 || defined(__AVR_ATxmega16D4__) \
139 || defined(__AVR_ATxmega32A4__) \
140 || defined(__AVR_ATxmega32A4U__) \
141 || defined(__AVR_ATxmega32C4__) \
142 || defined(__AVR_ATxmega32D4__) \
143 || defined(__AVR_ATxmega64A1U__) \
144 || defined(__AVR_ATxmega64A3__) \
145 || defined(__AVR_ATxmega64A3U__) \
146 || defined(__AVR_ATxmega64A4U__) \
147 || defined(__AVR_ATxmega64B1__) \
148 || defined(__AVR_ATxmega64B3__) \
149 || defined(__AVR_ATxmega64C3__) \
150 || defined(__AVR_ATxmega64D3__) \
151 || defined(__AVR_ATxmega64D4__) \
152 || defined(__AVR_ATxmega128A1__) \
153 || defined(__AVR_ATxmega128A1U__) \
154 || defined(__AVR_ATxmega128A3__) \
155 || defined(__AVR_ATxmega128A3U__) \
156 || defined(__AVR_ATxmega128A4U__) \
157 || defined(__AVR_ATxmega128B1__) \
158 || defined(__AVR_ATxmega128B3__) \
159 || defined(__AVR_ATxmega128C3__) \
160 || defined(__AVR_ATxmega128D3__) \
161 || defined(__AVR_ATxmega128D4__) \
162 || defined(__AVR_ATxmega192A3__) \
163 || defined(__AVR_ATxmega192A3U__) \
164 || defined(__AVR_ATxmega192C3__) \
165 || defined(__AVR_ATxmega192D3__) \
166 || defined(__AVR_ATxmega256A3__) \
167 || defined(__AVR_ATxmega256A3U__) \
168 || defined(__AVR_ATxmega256C3__) \
169 || defined(__AVR_ATxmega256D3__) \
170 || defined(__AVR_ATxmega256A3B__) \
171 || defined(__AVR_ATxmega256A3BU__) \
172 || defined(__AVR_ATxmega384C3__) \
173 || defined(__AVR_ATxmega384D3__)
174 
175 /*
176  wdt_enable(timeout) for xmega devices
177 ** write signature (CCP_IOREG_gc) that enables change of protected I/O
178  registers to the CCP register
179 ** At the same time,
180  1) set WDT change enable (WDT_CEN_bm)
181  2) enable WDT (WDT_ENABLE_bm)
182  3) set timeout (timeout)
183 ** Synchronization starts when ENABLE bit of WDT is set. So, wait till it
184  finishes (SYNCBUSY of STATUS register is automatically cleared after the
185  sync is finished).
186 */
187 #define wdt_enable(timeout) \
188 do { \
189 uint8_t temp; \
190 __asm__ __volatile__ ( \
191  "out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \
192  "sts %[wdt_reg], %[wdt_enable_timeout]" "\n\t" \
193  "1:lds %[tmp], %[wdt_status_reg]" "\n\t" \
194  "sbrc %[tmp], %[wdt_syncbusy_bit]" "\n\t" \
195  "rjmp 1b" "\n\t" \
196  "wdr" "\n\t" \
197  : \
198  : [ccp_reg] "M" _SFR_MEM_ADDR(CCP), \
199  [ioreg_cen_mask] "r" CCP_IOREG_gc, \
200  [wdt_reg] "M" _SFR_MEM_ADDR(WDT_CTRL), \
201  [wdt_enable_timeout] "r" (WDT_CEN_bm | WDT_ENABLE_bm | timeout), \
202  [wdt_status_reg] "M" _SFR_MEM_ADDR(WDT_STATUS), \
203  [wdt_syncbusy_bit] "I" WDT_SYNCBUSY_bm, \
204  [tmp] "r" temp \
205  : "r0" \
206 ) \
207 } while(0)
208 
209 #define wdt_disable() \
210 do { \
211 uint8_t temp; \
212 __asm__ __volatile__ ( \
213  "out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \
214  "lds %[tmp], %[wdt_reg]" "\n\t" \
215  "andi %[tmp], %[disable_mask]" "\n\t" \
216  "sts %[wdt_reg], %[wdt_disable]" "\n\t" \
217  : \
218  : [ccp_reg] "M" _SFR_MEM_ADDR(CCP), \
219  [ioreg_cen_mask] "r" CCP_IOREG_gc, \
220  [wdt_reg] "M" _SFR_MEM_ADDR(WDT_CTRL), \
221  [tmp] "r" temp, \
222  [disable_mask] "M" ~WDT_ENABLE_bm, \
223  [wdt_disable] "r" (temp | WDT_CEN_bm) \
224 )
225 
226 #elif defined(__AVR_AT90CAN32__) \
227 || defined(__AVR_AT90CAN64__) \
228 || defined(__AVR_AT90CAN128__) \
229 || defined(__AVR_AT90PWM1__) \
230 || defined(__AVR_AT90PWM2__) \
231 || defined(__AVR_AT90PWM216__) \
232 || defined(__AVR_AT90PWM2B__) \
233 || defined(__AVR_AT90PWM3__) \
234 || defined(__AVR_AT90PWM316__) \
235 || defined(__AVR_AT90PWM3B__) \
236 || defined(__AVR_AT90PWM161__) \
237 || defined(__AVR_AT90PWM81__) \
238 || defined(__AVR_AT90USB1286__) \
239 || defined(__AVR_AT90USB1287__) \
240 || defined(__AVR_AT90USB162__) \
241 || defined(__AVR_AT90USB646__) \
242 || defined(__AVR_AT90USB647__) \
243 || defined(__AVR_AT90USB82__) \
244 || defined(__AVR_ATmega128A__) \
245 || defined(__AVR_ATmega1280__) \
246 || defined(__AVR_ATmega1281__) \
247 || defined(__AVR_ATmega1284__) \
248 || defined(__AVR_ATmega1284P__) \
249 || defined(__AVR_ATmega128RFA1__) \
250 || defined(__AVR_ATmega1284RFR2__) \
251 || defined(__AVR_ATmega128RFR2__) \
252 || defined(__AVR_ATmega164__) \
253 || defined(__AVR_ATmega164A__) \
254 || defined(__AVR_ATmega164P__) \
255 || defined(__AVR_ATmega164PA__) \
256 || defined(__AVR_ATmega165__) \
257 || defined(__AVR_ATmega165A__) \
258 || defined(__AVR_ATmega165P__) \
259 || defined(__AVR_ATmega165PA__) \
260 || defined(__AVR_ATmega168__) \
261 || defined(__AVR_ATmega168A__) \
262 || defined(__AVR_ATmega168P__) \
263 || defined(__AVR_ATmega168PA__) \
264 || defined(__AVR_ATmega169__) \
265 || defined(__AVR_ATmega169A__) \
266 || defined(__AVR_ATmega169P__) \
267 || defined(__AVR_ATmega169PA__) \
268 || defined(__AVR_ATmega16HVA__) \
269 || defined(__AVR_ATmega16HVA2__) \
270 || defined(__AVR_ATmega16HVB__) \
271 || defined(__AVR_ATmega16HVBREVB__) \
272 || defined(__AVR_ATmega16M1__) \
273 || defined(__AVR_ATmega16U2__) \
274 || defined(__AVR_ATmega16U4__) \
275 || defined(__AVR_ATmega2560__) \
276 || defined(__AVR_ATmega2561__) \
277 || defined(__AVR_ATmega2564RFR2__) \
278 || defined(__AVR_ATmega256RFR2__) \
279 || defined(__AVR_ATmega32A__) \
280 || defined(__AVR_ATmega324__) \
281 || defined(__AVR_ATmega324A__) \
282 || defined(__AVR_ATmega324P__) \
283 || defined(__AVR_ATmega324PA__) \
284 || defined(__AVR_ATmega325__) \
285 || defined(__AVR_ATmega325A__) \
286 || defined(__AVR_ATmega325P__) \
287 || defined(__AVR_ATmega325PA__) \
288 || defined(__AVR_ATmega3250__) \
289 || defined(__AVR_ATmega3250A__) \
290 || defined(__AVR_ATmega3250P__) \
291 || defined(__AVR_ATmega3250PA__) \
292 || defined(__AVR_ATmega328__) \
293 || defined(__AVR_ATmega328P__) \
294 || defined(__AVR_ATmega329__) \
295 || defined(__AVR_ATmega329A__) \
296 || defined(__AVR_ATmega329P__) \
297 || defined(__AVR_ATmega329PA__) \
298 || defined(__AVR_ATmega3290__) \
299 || defined(__AVR_ATmega3290A__) \
300 || defined(__AVR_ATmega3290P__) \
301 || defined(__AVR_ATmega3290PA__) \
302 || defined(__AVR_ATmega32C1__) \
303 || defined(__AVR_ATmega32HVB__) \
304 || defined(__AVR_ATmega32HVBREVB__) \
305 || defined(__AVR_ATmega32M1__) \
306 || defined(__AVR_ATmega32U2__) \
307 || defined(__AVR_ATmega32U4__) \
308 || defined(__AVR_ATmega32U6__) \
309 || defined(__AVR_ATmega406__) \
310 || defined(__AVR_ATmega48__) \
311 || defined(__AVR_ATmega48A__) \
312 || defined(__AVR_ATmega48P__) \
313 || defined(__AVR_ATmega48PA__) \
314 || defined(__AVR_ATmega644RFR2__) \
315 || defined(__AVR_ATmega64RFR2__) \
316 || defined(__AVR_ATmega64A__) \
317 || defined(__AVR_ATmega640__) \
318 || defined(__AVR_ATmega644__) \
319 || defined(__AVR_ATmega644A__) \
320 || defined(__AVR_ATmega644P__) \
321 || defined(__AVR_ATmega644PA__) \
322 || defined(__AVR_ATmega645__) \
323 || defined(__AVR_ATmega645A__) \
324 || defined(__AVR_ATmega645P__) \
325 || defined(__AVR_ATmega6450__) \
326 || defined(__AVR_ATmega6450A__) \
327 || defined(__AVR_ATmega6450P__) \
328 || defined(__AVR_ATmega649__) \
329 || defined(__AVR_ATmega649A__) \
330 || defined(__AVR_ATmega6490__) \
331 || defined(__AVR_ATmega6490A__) \
332 || defined(__AVR_ATmega6490P__) \
333 || defined(__AVR_ATmega649P__) \
334 || defined(__AVR_ATmega64C1__) \
335 || defined(__AVR_ATmega64HVE__) \
336 || defined(__AVR_ATmega64M1__) \
337 || defined(__AVR_ATmega8A__) \
338 || defined(__AVR_ATmega88__) \
339 || defined(__AVR_ATmega88A__) \
340 || defined(__AVR_ATmega88P__) \
341 || defined(__AVR_ATmega88PA__) \
342 || defined(__AVR_ATmega8HVA__) \
343 || defined(__AVR_ATmega8U2__) \
344 || defined(__AVR_ATtiny48__) \
345 || defined(__AVR_ATtiny88__) \
346 || defined(__AVR_ATtiny87__) \
347 || defined(__AVR_ATtiny167__) \
348 || defined(__AVR_AT90SCR100__) \
349 || defined(__AVR_ATA6285__) \
350 || defined(__AVR_ATA6286__) \
351 || defined(__AVR_ATA6289__) \
352 || defined(__AVR_ATA5272__) \
353 || defined(__AVR_ATA5505__) \
354 || defined(__AVR_ATA5790__) \
355 || defined(__AVR_ATA5795__)
356 
357 /* Use STS instruction. */
358 
359 #define wdt_enable(value) \
360 __asm__ __volatile__ ( \
361  "in __tmp_reg__,__SREG__" "\n\t" \
362  "cli" "\n\t" \
363  "wdr" "\n\t" \
364  "sts %0,%1" "\n\t" \
365  "out __SREG__,__tmp_reg__" "\n\t" \
366  "sts %0,%2" "\n\t" \
367  : /* no outputs */ \
368  : "M" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), \
369  "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))), \
370  "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | \
371  _BV(WDE) | (value & 0x07)) ) \
372  : "r0" \
373 )
374 
375 #define wdt_disable() \
376 __asm__ __volatile__ ( \
377  "in __tmp_reg__, __SREG__" "\n\t" \
378  "cli" "\n\t" \
379  "sts %0, %1" "\n\t" \
380  "sts %0, __zero_reg__" "\n\t" \
381  "out __SREG__,__tmp_reg__" "\n\t" \
382  : /* no outputs */ \
383  : "M" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), \
384  "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) \
385  : "r0" \
386 )
387 
388 
389 #elif defined(__AVR_ATtiny4__) \
390 || defined(__AVR_ATtiny5__) \
391 || defined(__AVR_ATtiny9__) \
392 || defined(__AVR_ATtiny10__) \
393 || defined(__AVR_ATtiny20__) \
394 || defined(__AVR_ATtiny40__)
395 
396 #define wdt_enable(value) \
397 __asm__ __volatile__ ( \
398  "in __tmp_reg__,__SREG__" "\n\t" \
399  "cli" "\n\t" \
400  "wdr" "\n\t" \
401  "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" \
402  "out %[WDTREG],%[WDVALUE]" "\n\t" \
403  "out __SREG__,__tmp_reg__" "\n\t" \
404  : /* no outputs */ \
405  : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), \
406  [SIGNATURE] "r" ((uint8_t)0xD8), \
407  [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
408  [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) \
409  | _BV(WDE) | value)) \
410  : "r16" \
411 )
412 
413 #define wdt_disable() \
414 do { \
415 uint8_t temp_wd; \
416 __asm__ __volatile__ ( \
417  "in __tmp_reg__,__SREG__" "\n\t" \
418  "cli" "\n\t" \
419  "wdr" "\n\t" \
420  "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" \
421  "in %[TEMP_WD],%[WDTREG]" "\n\t" \
422  "cbr %[TEMP_WD],%[WDVALUE]" "\n\t" \
423  "out %[WDTREG],%[TEMP_WD]" "\n\t" \
424  "out __SREG__,__tmp_reg__" "\n\t" \
425  : /*no output */ \
426  : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), \
427  [SIGNATURE] "r" ((uint8_t)0xD8), \
428  [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
429  [TEMP_WD] "d" (temp_wd), \
430  [WDVALUE] "I" (1 << WDE) \
431  : "r16" \
432 ); \
433 }while(0)
434 
435 #else
436 
437 /* Use OUT instruction. */
438 
439 #define wdt_enable(value) \
440  __asm__ __volatile__ ( \
441  "in __tmp_reg__,__SREG__" "\n\t" \
442  "cli" "\n\t" \
443  "wdr" "\n\t" \
444  "out %0,%1" "\n\t" \
445  "out __SREG__,__tmp_reg__" "\n\t" \
446  "out %0,%2" \
447  : /* no outputs */ \
448  : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
449  "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))), \
450  "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | \
451  _BV(WDE) | (value & 0x07)) ) \
452  : "r0" \
453  )
454 
455 /**
456  \ingroup avr_watchdog
457  Disable the watchdog timer, if possible. This attempts to turn off the
458  Enable bit in the watchdog control register. See the datasheet for
459  details.
460 */
461 #define wdt_disable() \
462 __asm__ __volatile__ ( \
463  "in __tmp_reg__, __SREG__" "\n\t" \
464  "cli" "\n\t" \
465  "out %0, %1" "\n\t" \
466  "out %0, __zero_reg__" "\n\t" \
467  "out __SREG__,__tmp_reg__" "\n\t" \
468  : /* no outputs */ \
469  : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
470  "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) \
471  : "r0" \
472 )
473 
474 #endif
475 
476 
477 
478 /**
479  \ingroup avr_watchdog
480  Symbolic constants for the watchdog timeout. Since the watchdog
481  timer is based on a free-running RC oscillator, the times are
482  approximate only and apply to a supply voltage of 5 V. At lower
483  supply voltages, the times will increase. For older devices, the
484  times will be as large as three times when operating at Vcc = 3 V,
485  while the newer devices (e. g. ATmega128, ATmega8) only experience
486  a negligible change.
487 
488  Possible timeout values are: 15 ms, 30 ms, 60 ms, 120 ms, 250 ms,
489  500 ms, 1 s, 2 s. (Some devices also allow for 4 s and 8 s.)
490  Symbolic constants are formed by the prefix
491  \c WDTO_, followed by the time.
492 
493  Example that would select a watchdog timer expiry of approximately
494  500 ms:
495  \code
496  wdt_enable(WDTO_500MS);
497  \endcode
498 */
499 #define WDTO_15MS 0
500 
501 /** \ingroup avr_watchdog
502  See \c WDT0_15MS */
503 #define WDTO_30MS 1
504 
505 /** \ingroup avr_watchdog See
506  \c WDT0_15MS */
507 #define WDTO_60MS 2
508 
509 /** \ingroup avr_watchdog
510  See \c WDT0_15MS */
511 #define WDTO_120MS 3
512 
513 /** \ingroup avr_watchdog
514  See \c WDT0_15MS */
515 #define WDTO_250MS 4
516 
517 /** \ingroup avr_watchdog
518  See \c WDT0_15MS */
519 #define WDTO_500MS 5
520 
521 /** \ingroup avr_watchdog
522  See \c WDT0_15MS */
523 #define WDTO_1S 6
524 
525 /** \ingroup avr_watchdog
526  See \c WDT0_15MS */
527 #define WDTO_2S 7
528 
529 #if defined(__DOXYGEN__) || defined(WDP3)
530 
531 /** \ingroup avr_watchdog
532  See \c WDT0_15MS
533  Note: This is only available on the
534  ATtiny2313,
535  ATtiny24, ATtiny44, ATtiny84, ATtiny84A,
536  ATtiny25, ATtiny45, ATtiny85,
537  ATtiny261, ATtiny461, ATtiny861,
538  ATmega48, ATmega88, ATmega168,
539  ATmega48P, ATmega88P, ATmega168P, ATmega328P,
540  ATmega164P, ATmega324P, ATmega644P, ATmega644,
541  ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
542  ATmega8HVA, ATmega16HVA, ATmega32HVB,
543  ATmega406, ATmega1284P,
544  AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
545  AT90PWM81, AT90PWM161,
546  AT90USB82, AT90USB162,
547  AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
548  ATtiny48, ATtiny88.
549  */
550 #define WDTO_4S 8
551 
552 /** \ingroup avr_watchdog
553  See \c WDT0_15MS
554  Note: This is only available on the
555  ATtiny2313,
556  ATtiny24, ATtiny44, ATtiny84, ATtiny84A,
557  ATtiny25, ATtiny45, ATtiny85,
558  ATtiny261, ATtiny461, ATtiny861,
559  ATmega48, ATmega48A, ATmega48PA, ATmega88, ATmega168,
560  ATmega48P, ATmega88P, ATmega168P, ATmega328P,
561  ATmega164P, ATmega324P, ATmega644P, ATmega644,
562  ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
563  ATmega8HVA, ATmega16HVA, ATmega32HVB,
564  ATmega406, ATmega1284P,
565  ATmega2564RFR2, ATmega256RFR2, ATmega1284RFR2, ATmega128RFR2, ATmega644RFR2, ATmega64RFR2
566  AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
567  AT90PWM81, AT90PWM161,
568  AT90USB82, AT90USB162,
569  AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
570  ATtiny48, ATtiny88,
571  ATxmega16a4u, ATxmega32a4u,
572  ATxmega16c4, ATxmega32c4,
573  ATxmega128c3, ATxmega192c3, ATxmega256c3.
574  */
575 #define WDTO_8S 9
576 
577 #endif /* defined(__DOXYGEN__) || defined(WDP3) */
578 
579 
580 #endif /* _AVR_WDT_H_ */

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