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boot.h
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1/* Copyright (c) 2002,2003,2004,2005,2006,2007,2008,2009 Eric B. Weddington
2 All rights reserved.
3
4 Redistribution and use in source and binary forms, with or without
5 modification, are permitted provided that the following conditions are met:
6
7 * Redistributions of source code must retain the above copyright
8 notice, this list of conditions and the following disclaimer.
9 * Redistributions in binary form must reproduce the above copyright
10 notice, this list of conditions and the following disclaimer in
11 the documentation and/or other materials provided with the
12 distribution.
13 * Neither the name of the copyright holders nor the names of
14 contributors may be used to endorse or promote products derived
15 from this software without specific prior written permission.
16
17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 POSSIBILITY OF SUCH DAMAGE. */
28
29/* $Id$ */
30
31#ifndef _AVR_BOOT_H_
32#define _AVR_BOOT_H_ 1
33
34/** \file */
35/** \defgroup avr_boot <avr/boot.h>: Bootloader Support Utilities
36 \code
37 #include <avr/io.h>
38 #include <avr/boot.h>
39 \endcode
40
41 The macros in this module provide a C language interface to the
42 bootloader support functionality of certain AVR processors. These
43 macros are designed to work with all sizes of flash memory.
44
45 Global interrupts are not automatically disabled for these macros. It
46 is left up to the programmer to do this. See the code example below.
47 Also see the processor datasheet for caveats on having global interrupts
48 enabled during writing of the Flash.
49
50 \note Not all AVR processors provide bootloader support. See your
51 processor datasheet to see if it provides bootloader support.
52
53 \par API Usage Example
54 The following code shows typical usage of the boot API.
55
56 \code
57 #include <stdint.h>
58 #include <avr/interrupt.h>
59 #include <avr/pgmspace.h>
60
61 void boot_program_page (uint32_t page, uint8_t *buf)
62 {
63 // Disable interrupts.
64 uint8_t sreg = SREG;
65 cli();
66
67 eeprom_busy_wait ();
68
69 boot_page_erase (page);
70 boot_spm_busy_wait (); // Wait until the memory is erased.
71
72 for (uint16_t i = 0; i < SPM_PAGESIZE; i += 2)
73 {
74 // Set up little-endian word.
75 uint16_t w = *buf++;
76 w += (*buf++) << 8;
77
78 boot_page_fill (page + i, w);
79 }
80
81 boot_page_write (page); // Store buffer in flash page.
82 boot_spm_busy_wait(); // Wait until the memory is written.
83
84 // Reenable RWW-section again. We need this if we want to jump back
85 // to the application after bootloading.
86 boot_rww_enable ();
87
88 // Re-enable interrupts (if they were ever enabled).
89 SREG = sreg;
90 }\endcode */
91
92#include <avr/eeprom.h>
93#include <avr/io.h>
94#include <inttypes.h>
95#include <limits.h>
96
97/* Check for SPM Control Register in processor. */
98#if defined (SPMCSR)
99# define __SPM_REG SPMCSR
100#else
101# if defined (SPMCR)
102# define __SPM_REG SPMCR
103# else
104# error AVR processor does not provide bootloader support!
105# endif
106#endif
107
108
109/* Check for SPM Enable bit. */
110#if defined(SPMEN)
111# define __SPM_ENABLE SPMEN
112#elif defined(SELFPRGEN)
113# define __SPM_ENABLE SELFPRGEN
114#else
115# error Cannot find SPM Enable bit definition!
116#endif
117
118/** \ingroup avr_boot
119 \def BOOTLOADER_SECTION
120
121 Used to declare a function or variable to be placed into a
122 new section called .bootloader. This section and its contents
123 can then be relocated to any address (such as the bootloader
124 NRWW area) at link-time. */
125
126#define BOOTLOADER_SECTION __attribute__ ((__section__(".bootloader")))
127
128#ifndef __DOXYGEN__
129/* Create common bit definitions. */
130#ifdef ASB
131#define __COMMON_ASB ASB
132#else
133#define __COMMON_ASB RWWSB
134#endif
135
136#ifdef ASRE
137#define __COMMON_ASRE ASRE
138#else
139#define __COMMON_ASRE RWWSRE
140#endif
141
142/* Define the bit positions of the Boot Lock Bits. */
143
144#define BLB12 5
145#define BLB11 4
146#define BLB02 3
147#define BLB01 2
148#endif /* __DOXYGEN__ */
149
150/** \ingroup avr_boot
151 \def boot_spm_interrupt_enable()
152 Enable the SPM interrupt. */
153
154#define boot_spm_interrupt_enable() (__SPM_REG |= (uint8_t)_BV(SPMIE))
155
156/** \ingroup avr_boot
157 \def boot_spm_interrupt_disable()
158 Disable the SPM interrupt. */
159
160#define boot_spm_interrupt_disable() (__SPM_REG &= (uint8_t)~_BV(SPMIE))
161
162/** \ingroup avr_boot
163 \def boot_is_spm_interrupt()
164 Check if the SPM interrupt is enabled. */
165
166#define boot_is_spm_interrupt() (__SPM_REG & (uint8_t)_BV(SPMIE))
167
168/** \ingroup avr_boot
169 \def boot_rww_busy()
170 Check if the RWW section is busy. */
171
172#define boot_rww_busy() (__SPM_REG & (uint8_t)_BV(__COMMON_ASB))
173
174/** \ingroup avr_boot
175 \def boot_spm_busy()
176 Check if the SPM instruction is busy. */
177
178#define boot_spm_busy() (__SPM_REG & (uint8_t)_BV(__SPM_ENABLE))
179
180/** \ingroup avr_boot
181 \def boot_spm_busy_wait()
182 Wait while the SPM instruction is busy. */
183
184#define boot_spm_busy_wait() do{}while(boot_spm_busy())
185
186#ifndef __DOXYGEN__
187#define __BOOT_PAGE_ERASE (_BV(__SPM_ENABLE) | _BV(PGERS))
188#define __BOOT_PAGE_WRITE (_BV(__SPM_ENABLE) | _BV(PGWRT))
189#define __BOOT_PAGE_FILL _BV(__SPM_ENABLE)
190#define __BOOT_RWW_ENABLE (_BV(__SPM_ENABLE) | _BV(__COMMON_ASRE))
191#if defined(BLBSET)
192#define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(BLBSET))
193#elif defined(RFLB) /* Some devices have RFLB defined instead of BLBSET. */
194#define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(RFLB))
195#elif defined(RWFLB) /* Some devices have RWFLB defined instead of BLBSET. */
196#define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(RWFLB))
197#endif
198
199#define __boot_page_fill_normal(address, data) \
200(__extension__({ \
201 if (_SFR_IO_REG_P(__SPM_REG)) \
202 __asm__ __volatile__ ( \
203 "movw r0, %3" "\n\t" \
204 "out %0, %1" "\n\t" \
205 "spm" "\n\t" \
206 "clr __zero_reg__" \
207 : \
208 : "i" (_SFR_IO_ADDR(__SPM_REG)), \
209 "r" ((uint8_t)(__BOOT_PAGE_FILL)), \
210 "z" ((uint16_t)(address)), \
211 "r" ((uint16_t)(data)) \
212 : "r0"); \
213 else \
214 __asm__ __volatile__ ( \
215 "movw r0, %3" "\n\t" \
216 "sts %0, %1" "\n\t" \
217 "spm" "\n\t" \
218 "clr __zero_reg__" \
219 : \
220 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
221 "r" ((uint8_t)(__BOOT_PAGE_FILL)), \
222 "z" ((uint16_t)(address)), \
223 "r" ((uint16_t)(data)) \
224 : "r0"); \
225}))
226
227#define __boot_page_fill_alternate(address, data)\
228(__extension__({ \
229 __asm__ __volatile__ \
230 ( \
231 "movw r0, %3" "\n\t" \
232 "sts %0, %1" "\n\t" \
233 "spm" "\n\t" \
234 ".word 0xffff" "\n\t" \
235 "nop" "\n\t" \
236 "clr __zero_reg__" \
237 : \
238 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
239 "r" ((uint8_t)(__BOOT_PAGE_FILL)), \
240 "z" ((uint16_t)(address)), \
241 "r" ((uint16_t)(data)) \
242 : "r0" \
243 ); \
244}))
245
246#define __boot_page_fill_extended(address, data) \
247(__extension__({ \
248 __asm__ __volatile__ \
249 ( \
250 "movw r0, %4" "\n\t" \
251 "movw r30, %A3" "\n\t" \
252 "out %1, %C3" "\n\t" \
253 "sts %0, %2" "\n\t" \
254 "spm" "\n\t" \
255 "clr __zero_reg__" \
256 : \
257 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
258 "i" (_SFR_IO_ADDR(RAMPZ)), \
259 "r" ((uint8_t)(__BOOT_PAGE_FILL)), \
260 "r" ((uint32_t)(address)), \
261 "r" ((uint16_t)(data)) \
262 : "r0", "r30", "r31" \
263 ); \
264}))
265
266#define __boot_page_erase_normal(address) \
267(__extension__({ \
268 if (_SFR_IO_REG_P(__SPM_REG)) \
269 __asm__ __volatile__ ( \
270 "out %0, %1" "\n\t" \
271 "spm" \
272 : \
273 : "i" (_SFR_IO_ADDR(__SPM_REG)), \
274 "r" ((uint8_t)(__BOOT_PAGE_ERASE)), \
275 "z" ((uint16_t)(address))); \
276 else \
277 __asm__ __volatile__ ( \
278 "sts %0, %1" "\n\t" \
279 "spm" \
280 : \
281 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
282 "r" ((uint8_t)(__BOOT_PAGE_ERASE)), \
283 "z" ((uint16_t)(address))); \
284}))
285
286#define __boot_page_erase_alternate(address) \
287(__extension__({ \
288 __asm__ __volatile__ \
289 ( \
290 "sts %0, %1" "\n\t" \
291 "spm" "\n\t" \
292 ".word 0xffff" "\n\t" \
293 "nop" \
294 : \
295 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
296 "r" ((uint8_t)(__BOOT_PAGE_ERASE)), \
297 "z" ((uint16_t)(address)) \
298 ); \
299}))
300
301#define __boot_page_erase_extended(address) \
302(__extension__({ \
303 __asm__ __volatile__ \
304 ( \
305 "movw r30, %A3" "\n\t" \
306 "out %1, %C3" "\n\t" \
307 "sts %0, %2" "\n\t" \
308 "spm" \
309 : \
310 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
311 "i" (_SFR_IO_ADDR(RAMPZ)), \
312 "r" ((uint8_t)(__BOOT_PAGE_ERASE)), \
313 "r" ((uint32_t)(address)) \
314 : "r30", "r31" \
315 ); \
316}))
317
318#define __boot_page_write_normal(address) \
319(__extension__({ \
320 if (_SFR_IO_REG_P(__SPM_REG)) \
321 __asm__ __volatile__ ( \
322 "out %0, %1" "\n\t" \
323 "spm" \
324 : \
325 : "i" (_SFR_IO_ADDR(__SPM_REG)), \
326 "r" ((uint8_t)(__BOOT_PAGE_WRITE)), \
327 "z" ((uint16_t)(address))); \
328 else \
329 __asm__ __volatile__ ( \
330 "sts %0, %1" "\n\t" \
331 "spm" \
332 : \
333 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
334 "r" ((uint8_t)(__BOOT_PAGE_WRITE)), \
335 "z" ((uint16_t)(address))); \
336}))
337
338#define __boot_page_write_alternate(address) \
339(__extension__({ \
340 __asm__ __volatile__ \
341 ( \
342 "sts %0, %1" "\n\t" \
343 "spm" "\n\t" \
344 ".word 0xffff" "\n\t" \
345 "nop" \
346 : \
347 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
348 "r" ((uint8_t)(__BOOT_PAGE_WRITE)), \
349 "z" ((uint16_t)(address)) \
350 ); \
351}))
352
353#define __boot_page_write_extended(address) \
354(__extension__({ \
355 __asm__ __volatile__ \
356 ( \
357 "movw r30, %A3" "\n\t" \
358 "out %1, %C3" "\n\t" \
359 "sts %0, %2" "\n\t" \
360 "spm" \
361 : \
362 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
363 "i" (_SFR_IO_ADDR(RAMPZ)), \
364 "r" ((uint8_t)(__BOOT_PAGE_WRITE)), \
365 "r" ((uint32_t)(address)) \
366 : "r30", "r31" \
367 ); \
368}))
369
370#define __boot_rww_enable() \
371(__extension__({ \
372 __asm__ __volatile__ \
373 ( \
374 "sts %0, %1" "\n\t" \
375 "spm" \
376 : \
377 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
378 "r" ((uint8_t)(__BOOT_RWW_ENABLE)) \
379 ); \
380}))
381
382#define __boot_rww_enable_alternate() \
383(__extension__({ \
384 __asm__ __volatile__ \
385 ( \
386 "sts %0, %1" "\n\t" \
387 "spm" "\n\t" \
388 ".word 0xffff" "\n\t" \
389 "nop" \
390 : \
391 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
392 "r" ((uint8_t)(__BOOT_RWW_ENABLE)) \
393 ); \
394}))
395
396/* From the mega16/mega128 data sheets (maybe others):
397
398 Bits by SPM To set the Boot Loader Lock bits, write the desired data to
399 R0, write "X0001001" to SPMCR and execute SPM within four clock cycles
400 after writing SPMCR. The only accessible Lock bits are the Boot Lock bits
401 that may prevent the Application and Boot Loader section from any
402 software update by the MCU.
403
404 If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit
405 will be programmed if an SPM instruction is executed within four cycles
406 after BLBSET and SPMEN (or SELFPRGEN) are set in SPMCR. The Z-pointer is
407 don't care during this operation, but for future compatibility it is
408 recommended to load the Z-pointer with $0001 (same as used for reading the
409 Lock bits). For future compatibility It is also recommended to set bits 7,
410 6, 1, and 0 in R0 to 1 when writing the Lock bits. When programming the
411 Lock bits the entire Flash can be read during the operation. */
412
413#define __boot_lock_bits_set(lock_bits) \
414(__extension__({ \
415 uint8_t value = (uint8_t)(~(lock_bits)); \
416 __asm__ __volatile__ \
417 ( \
418 "ldi r30, 1" "\n\t" \
419 "ldi r31, 0" "\n\t" \
420 "mov r0, %2" "\n\t" \
421 "sts %0, %1" "\n\t" \
422 "spm" \
423 : \
424 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
425 "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \
426 "r" (value) \
427 : "r0", "r30", "r31" \
428 ); \
429}))
430
431#define __boot_lock_bits_set_alternate(lock_bits) \
432(__extension__({ \
433 uint8_t value = (uint8_t)(~(lock_bits)); \
434 __asm__ __volatile__ \
435 ( \
436 "ldi r30, 1" "\n\t" \
437 "ldi r31, 0" "\n\t" \
438 "mov r0, %2" "\n\t" \
439 "sts %0, %1" "\n\t" \
440 "spm" "\n\t" \
441 ".word 0xffff" "\n\t" \
442 "nop" \
443 : \
444 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
445 "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \
446 "r" (value) \
447 : "r0", "r30", "r31" \
448 ); \
449}))
450#endif /* __DOXYGEN__ */
451
452/*
453 Reading lock and fuse bits:
454
455 Similarly to writing the lock bits above, set BLBSET and SPMEN (or
456 SELFPRGEN) bits in __SPMREG, and then (within four clock cycles) issue an
457 LPM instruction.
458
459 Z address: contents:
460 0x0000 low fuse bits
461 0x0001 lock bits
462 0x0002 extended fuse bits
463 0x0003 high fuse bits
464
465 Sounds confusing, doesn't it?
466
467 Unlike the macros in pgmspace.h, no need to care for non-enhanced
468 cores here as these old cores do not provide SPM support anyway.
469 */
470
471/** \ingroup avr_boot
472 \def GET_LOW_FUSE_BITS
473 address to read the low fuse bits, using boot_lock_fuse_bits_get
474 */
475#define GET_LOW_FUSE_BITS (0x0000)
476/** \ingroup avr_boot
477 \def GET_LOCK_BITS
478 address to read the lock bits, using boot_lock_fuse_bits_get
479 */
480#define GET_LOCK_BITS (0x0001)
481/** \ingroup avr_boot
482 \def GET_EXTENDED_FUSE_BITS
483 address to read the extended fuse bits, using boot_lock_fuse_bits_get
484 */
485#define GET_EXTENDED_FUSE_BITS (0x0002)
486/** \ingroup avr_boot
487 \def GET_HIGH_FUSE_BITS
488 address to read the high fuse bits, using boot_lock_fuse_bits_get
489 */
490#define GET_HIGH_FUSE_BITS (0x0003)
491
492/** \ingroup avr_boot
493 \def boot_lock_fuse_bits_get(address)
494
495 Read the lock or fuse bits at \c address.
496
497 Parameter \c address can be any of GET_LOW_FUSE_BITS,
498 GET_LOCK_BITS, GET_EXTENDED_FUSE_BITS, or GET_HIGH_FUSE_BITS.
499
500 \note The lock and fuse bits returned are the physical values,
501 i.e. a bit returned as 0 means the corresponding fuse or lock bit
502 is programmed.
503 */
504#define boot_lock_fuse_bits_get(address) \
505(__extension__({ \
506 uint8_t __result; \
507 __asm__ __volatile__ \
508 ( \
509 "sts %1, %2\n\t" \
510 "lpm %0, Z\n\t" \
511 : "=r" (__result) \
512 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
513 "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \
514 "z" ((uint16_t)(address)) \
515 ); \
516 __result; \
517}))
518
519#ifndef __DOXYGEN__
520# if defined(SIGRD)
521# define __BOOT_SIGROW_READ (_BV(__SPM_ENABLE) | _BV(SIGRD))
522# elif defined(RSIG)
523# define __BOOT_SIGROW_READ (_BV(__SPM_ENABLE) | _BV(RSIG))
524# endif
525#endif
526
527/** \ingroup avr_boot
528 \def boot_signature_byte_get(address)
529
530 Read the Signature Row byte at \c address. For some MCU types,
531 this function can also retrieve the factory-stored oscillator
532 calibration bytes.
533
534 Parameter \c address can be 0-0x1f as documented by the datasheet.
535 \note The values are MCU type dependent.
536*/
537
538#define boot_signature_byte_get(addr) \
539 (__extension__({ \
540 uint8_t __result; \
541 __asm__ __volatile__ \
542 ( \
543 "sts %1, %2" "\n\t" \
544 "lpm %0, Z" \
545 : "=r" (__result) \
546 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
547 "r" ((uint8_t)(__BOOT_SIGROW_READ)), \
548 "z" ((uint16_t)(addr)) \
549 ); \
550 __result; \
551}))
552
553/** \ingroup avr_boot
554 \def boot_page_fill(address, data)
555
556 Fill the bootloader temporary page buffer for flash
557 address with data word.
558
559 \note The address is a byte address. The data is a word. The AVR
560 writes data to the buffer a word at a time, but addresses the buffer
561 per byte! So, increment your address by 2 between calls, and send 2
562 data bytes in a word format! The LSB of the data is written to the lower
563 address; the MSB of the data is written to the higher address.*/
564
565/** \ingroup avr_boot
566 \def boot_page_erase(address)
567
568 Erase the flash page that contains address.
569
570 \note address is a byte address in flash, not a word address. */
571
572/** \ingroup avr_boot
573 \def boot_page_write(address)
574
575 Write the bootloader temporary page buffer
576 to flash page that contains address.
577
578 \note address is a byte address in flash, not a word address. */
579
580/** \ingroup avr_boot
581 \def boot_rww_enable()
582
583 Enable the Read-While-Write memory section. */
584
585/** \ingroup avr_boot
586 \def boot_lock_bits_set(lock_bits)
587
588 Set the bootloader lock bits.
589
590 \param lock_bits A mask of which Boot Loader Lock Bits to set.
591
592 \note In this context, a 'set bit' will be written to a zero value.
593 Note also that only BLBxx bits can be programmed by this command.
594
595 For example, to disallow the SPM instruction from writing to the Boot
596 Loader memory section of flash, you would use this macro as such:
597
598 \code
599 boot_lock_bits_set (_BV (BLB11));
600 \endcode
601
602 \note Like any lock bits, the Boot Loader Lock Bits, once set,
603 cannot be cleared again except by a chip erase which will in turn
604 also erase the boot loader itself. */
605
606/* Normal versions of the macros use 16-bit addresses.
607 Extended versions of the macros use 32-bit addresses.
608 Alternate versions of the macros use 16-bit addresses and require special
609 instruction sequences after LPM.
610
611 FLASHEND is defined in the ioXXXX.h file.
612 USHRT_MAX is defined in <limits.h>. */
613
614#if defined(__AVR_ATmega161__) || defined(__AVR_ATmega163__) \
615 || defined(__AVR_ATmega323__)
616
617/* Alternate: ATmega161/163/323 and 16 bit address */
618#define boot_page_fill(address, data) __boot_page_fill_alternate(address, data)
619#define boot_page_erase(address) __boot_page_erase_alternate(address)
620#define boot_page_write(address) __boot_page_write_alternate(address)
621#define boot_rww_enable() __boot_rww_enable_alternate()
622#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set_alternate(lock_bits)
623
624#elif (FLASHEND > USHRT_MAX)
625
626/* Extended: >16 bit address */
627#define boot_page_fill(address, data) __boot_page_fill_extended(address, data)
628#define boot_page_erase(address) __boot_page_erase_extended(address)
629#define boot_page_write(address) __boot_page_write_extended(address)
630#define boot_rww_enable() __boot_rww_enable()
631#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits)
632
633#else
634
635/* Normal: 16 bit address */
636#define boot_page_fill(address, data) __boot_page_fill_normal(address, data)
637#define boot_page_erase(address) __boot_page_erase_normal(address)
638#define boot_page_write(address) __boot_page_write_normal(address)
639#define boot_rww_enable() __boot_rww_enable()
640#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits)
641
642#endif
643
644/** \ingroup avr_boot
645
646 Same as boot_page_fill() except it waits for eeprom and spm operations to
647 complete before filling the page. */
648
649#define boot_page_fill_safe(address, data) \
650do { \
651 boot_spm_busy_wait(); \
652 eeprom_busy_wait(); \
653 boot_page_fill(address, data); \
654} while (0)
655
656/** \ingroup avr_boot
657
658 Same as boot_page_erase() except it waits for eeprom and spm operations to
659 complete before erasing the page. */
660
661#define boot_page_erase_safe(address) \
662do { \
663 boot_spm_busy_wait(); \
664 eeprom_busy_wait(); \
665 boot_page_erase (address); \
666} while (0)
667
668/** \ingroup avr_boot
669
670 Same as boot_page_write() except it waits for eeprom and spm operations to
671 complete before writing the page. */
672
673#define boot_page_write_safe(address) \
674do { \
675 boot_spm_busy_wait(); \
676 eeprom_busy_wait(); \
677 boot_page_write (address); \
678} while (0)
679
680/** \ingroup avr_boot
681
682 Same as boot_rww_enable() except waits for eeprom and spm operations to
683 complete before enabling the RWW mameory. */
684
685#define boot_rww_enable_safe() \
686do { \
687 boot_spm_busy_wait(); \
688 eeprom_busy_wait(); \
689 boot_rww_enable(); \
690} while (0)
691
692/** \ingroup avr_boot
693
694 Same as boot_lock_bits_set() except waits for eeprom and spm operations to
695 complete before setting the lock bits. */
696
697#define boot_lock_bits_set_safe(lock_bits) \
698do { \
699 boot_spm_busy_wait(); \
700 eeprom_busy_wait(); \
701 boot_lock_bits_set (lock_bits); \
702} while (0)
703
704#endif /* _AVR_BOOT_H_ */
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