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power.h
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1/* Copyright (c) 2006, 2007, 2008 Eric B. Weddington
2 Copyright (c) 2011 Frédéric Nadeau
3 All rights reserved.
4
5 Redistribution and use in source and binary forms, with or without
6 modification, are permitted provided that the following conditions are met:
7
8 * Redistributions of source code must retain the above copyright
9 notice, this list of conditions and the following disclaimer.
10 * Redistributions in binary form must reproduce the above copyright
11 notice, this list of conditions and the following disclaimer in
12 the documentation and/or other materials provided with the
13 distribution.
14 * Neither the name of the copyright holders nor the names of
15 contributors may be used to endorse or promote products derived
16 from this software without specific prior written permission.
17
18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
22 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 POSSIBILITY OF SUCH DAMAGE. */
29
30/* $Id$ */
31
32#ifndef _AVR_POWER_H_
33#define _AVR_POWER_H_ 1
34
35#include <avr/io.h>
36#include <stdint.h>
37
38#ifndef __DOXYGEN__
39#ifndef __ATTR_ALWAYS_INLINE__
40#define __ATTR_ALWAYS_INLINE__ __inline__ __attribute__((__always_inline__))
41#endif
42#endif /* ! DOXYGEN */
43
44/** \file */
45/** \defgroup avr_power <avr/power.h>: Power Reduction Management
46
47\code #include <avr/power.h>\endcode
48
49Many AVRs contain a Power Reduction Register (PRR) or Registers (PRRx) that
50allow you to reduce power consumption by disabling or enabling various on-board
51peripherals as needed. Some devices have the XTAL Divide Control Register
52(XDIV) which offer similar functionality as System Clock Prescale
53Register (CLKPR).
54
55There are many macros in this header file that provide an easy interface
56to enable or disable on-board peripherals to reduce power. See the table below.
57
58\note Not all AVR devices have a Power Reduction Register (for example
59the ATmega8). On those devices without a Power Reduction Register, the
60power reduction macros are not available..
61
62\note Not all AVR devices contain the same peripherals (for example, the LCD
63interface), or they will be named differently (for example, USART and
64USART0). Please consult your device's datasheet, or the header file, to
65find out which macros are applicable to your device.
66
67\note For device using the XTAL Divide Control Register (XDIV), when prescaler
68is used, Timer/Counter0 can only be used in asynchronous mode. Keep in mind
69that Timer/Counter0 source shall be less than ¼th of peripheral clock.
70Therefore, when using a typical 32.768 kHz crystal, one shall not scale
71the clock below 131.072 kHz.
72
73\anchor avr_powermacros
74<small>
75<table>
76 <caption>Power Macros</caption>
77 <tr>
78 <th>Power Macro
79 <th>Description
80 </tr>
81 <tr>
82 <td>\c power_aca_disable()</td>
83 <td>Disable the Analog Comparator on PortA</td>
84 </tr>
85 <tr>
86 <td>\c power_aca_enable()</td>
87 <td>Enable the Analog Comparator on PortA</td>
88 </tr>
89 <tr>
90 <td>\c power_adc_enable()</td>
91 <td>Enable the Analog to Digital Converter module</td>
92 </tr>
93 <tr>
94 <td>\c power_adc_disable()</td>
95 <td>Disable the Analog to Digital Converter module</td>
96 </tr>
97 <tr>
98 <td>\c power_adca_disable()</td>
99 <td>Disable the Analog to Digital Converter module on PortA</td>
100 </tr>
101 <tr>
102 <td>\c power_adca_enable()</td>
103 <td>Enable the Analog to Digital Converter module on PortA</td>
104 </tr>
105 <tr>
106 <td>\c power_evsys_disable()</td>
107 <td>Disable the EVSYS module</td>
108 </tr>
109 <tr>
110 <td>\c power_evsys_enable()</td>
111 <td>Enable the EVSYS module</td>
112 </tr>
113 <tr>
114 <td>\c power_hiresc_disable()</td>
115 <td>Disable the HIRES module on PortC</td>
116 </tr>
117 <tr>
118 <td>\c power_hiresc_enable()</td>
119 <td>Enable the HIRES module on PortC</td>
120 </tr>
121 <tr>
122 <td>\c power_lcd_enable()</td>
123 <td>Enable the LCD module</td>
124 </tr>
125 <tr>
126 <td>\c power_lcd_disable()</td>
127 <td>Disable the LCD module</td>
128 </tr>
129 <tr>
130 <td>\c power_pga_enable()</td>
131 <td>Enable the Programmable Gain Amplifier module</td>
132 </tr>
133 <tr>
134 <td>\c power_pga_disable()</td>
135 <td>Disable the Programmable Gain Amplifier module</td>
136 </tr>
137 <tr>
138 <td>\c power_pscr_enable()</td>
139 <td>Enable the Reduced Power Stage Controller module</td>
140 </tr>
141 <tr>
142 <td>\c power_pscr_disable()</td>
143 <td>Disable the Reduced Power Stage Controller module</td>
144 </tr>
145 <tr>
146 <td>\c power_psc0_enable()</td>
147 <td>Enable the Power Stage Controller 0 module</td>
148 </tr>
149 <tr>
150 <td>\c power_psc0_disable()</td>
151 <td>Disable the Power Stage Controller 0 module</td>
152 </tr>
153 <tr>
154 <td>\c power_psc1_enable()</td>
155 <td>Enable the Power Stage Controller 1 module</td>
156 </tr>
157 <tr>
158 <td>\c power_psc1_disable()</td>
159 <td>Disable the Power Stage Controller 1 module</td>
160 </tr>
161 <tr>
162 <td>\c power_psc2_enable()</td>
163 <td>Enable the Power Stage Controller 2 module</td>
164 </tr>
165 <tr>
166 <td>\c power_psc2_disable()</td>
167 <td>Disable the Power Stage Controller 2 module</td>
168 </tr>
169 <tr>
170 <td>\c power_ram0_enable()</td>
171 <td>Enable the SRAM block 0</td>
172 </tr>
173 <tr>
174 <td>\c power_ram0_disable()</td>
175 <td>Disable the SRAM block 0</td>
176 </tr>
177 <tr>
178 <td>\c power_ram1_enable()</td>
179 <td>Enable the SRAM block 1</td>
180 </tr>
181 <tr>
182 <td>\c power_ram1_disable()</td>
183 <td>Disable the SRAM block 1</td>
184 </tr>
185 <tr>
186 <td>\c power_ram2_enable()</td>
187 <td>Enable the SRAM block 2</td>
188 </tr>
189 <tr>
190 <td>\c power_ram2_disable()</td>
191 <td>Disable the SRAM block 2</td>
192 </tr>
193 <tr>
194 <td>\c power_ram3_enable()</td>
195 <td>Enable the SRAM block 3</td>
196 </tr>
197 <tr>
198 <td>\c power_ram3_disable()</td>
199 <td>Disable the SRAM block 3</td>
200 </tr>
201 <tr>
202 <td>\c power_rtc_disable()</td>
203 <td>Disable the RTC module</td>
204 </tr>
205 <tr>
206 <td>\c power_rtc_enable()</td>
207 <td>Enable the RTC module</td>
208 </tr>
209 <tr>
210 <td>\c power_spi_enable()</td>
211 <td>Enable the Serial Peripheral Interface module</td>
212 </tr>
213 <tr>
214 <td>\c power_spi_disable()</td>
215 <td>Disable the Serial Peripheral Interface module</td>
216 </tr>
217 <tr>
218 <td>\c power_spic_disable()</td>
219 <td>Disable the SPI module on PortC</td>
220 </tr>
221 <tr>
222 <td>\c power_spic_enable()</td>
223 <td>Enable the SPI module on PortC</td>
224 </tr>
225 <tr>
226 <td>\c power_spid_disable()</td>
227 <td>Disable the SPI module on PortD</td>
228 </tr>
229 <tr>
230 <td>\c power_spid_enable()</td>
231 <td>Enable the SPI module on PortD</td>
232 </tr>
233 <tr>
234 <td>\c power_tc0c_disable()</td>
235 <td>Disable the TC0 module on PortC</td>
236 </tr>
237 <tr>
238 <td>\c power_tc0c_enable()</td>
239 <td>Enable the TC0 module on PortC</td>
240 </tr>
241 <tr>
242 <td>\c power_tc0d_disable()</td>
243 <td>Disable the TC0 module on PortD</td>
244 </tr>
245 <tr>
246 <td>\c power_tc0d_enable()</td>
247 <td>Enable the TC0 module on PortD</td>
248 </tr>
249 <tr>
250 <td>\c power_tc0e_disable()</td>
251 <td>Disable the TC0 module on PortE</td>
252 </tr>
253 <tr>
254 <td>\c power_tc0e_enable()</td>
255 <td>Enable the TC0 module on PortE</td>
256 </tr>
257 <tr>
258 <td>\c power_tc0f_disable()</td>
259 <td>Disable the TC0 module on PortF</td>
260 </tr>
261 <tr>
262 <td>\c power_tc0f_enable()</td>
263 <td>Enable the TC0 module on PortF</td>
264 </tr>
265 <tr>
266 <td>\c power_tc1c_disable()</td>
267 <td>Disable the TC1 module on PortC</td>
268 </tr>
269 <tr>
270 <td>\c power_tc1c_enable()</td>
271 <td>Enable the TC1 module on PortC</td>
272 </tr>
273 <tr>
274 <td>\c power_twic_disable()</td>
275 <td>Disable the Two Wire Interface module on PortC</td>
276 </tr>
277 <tr>
278 <td>\c power_twic_enable()</td>
279 <td>Enable the Two Wire Interface module on PortC</td>
280 </tr>
281 <tr>
282 <td>\c power_twie_disable()</td>
283 <td>Disable the Two Wire Interface module on PortE</td>
284 </tr>
285 <tr>
286 <td>\c power_twie_enable()</td>
287 <td>Enable the Two Wire Interface module on PortE</td>
288 </tr>
289 <tr>
290 <td>\c power_timer0_enable()</td>
291 <td>Enable the Timer 0 module</td>
292 </tr>
293 <tr>
294 <td>\c power_timer0_disable()</td>
295 <td>Disable the Timer 0 module</td>
296 </tr>
297 <tr>
298 <td>\c power_timer1_enable()</td>
299 <td>Enable the Timer 1 module</td>
300 </tr>
301 <tr>
302 <td>\c power_timer1_disable()</td>
303 <td>Disable the Timer 1 module</td>
304 </tr>
305 <tr>
306 <td>\c power_timer2_enable()</td>
307 <td>Enable the Timer 2 module</td>
308 </tr>
309 <tr>
310 <td>\c power_timer2_disable()</td>
311 <td>Disable the Timer 2 module</td>
312 </tr>
313 <tr>
314 <td>\c power_timer3_enable()</td>
315 <td>Enable the Timer 3 module</td>
316 </tr>
317 <tr>
318 <td>\c power_timer3_disable()</td>
319 <td>Disable the Timer 3 module</td>
320 </tr>
321 <tr>
322 <td>\c power_timer4_enable()</td>
323 <td>Enable the Timer 4 module</td>
324 </tr>
325 <tr>
326 <td>\c power_timer4_disable()</td>
327 <td>Disable the Timer 4 module</td>
328 </tr>
329 <tr>
330 <td>\c power_timer5_enable()</td>
331 <td>Enable the Timer 5 module</td>
332 </tr>
333 <tr>
334 <td>\c power_timer5_disable()</td>
335 <td>Disable the Timer 5 module</td>
336 </tr>
337 <tr>
338 <td>\c power_twi_enable()</td>
339 <td>Enable the Two Wire Interface module</td>
340 </tr>
341 <tr>
342 <td>\c power_twi_disable()</td>
343 <td>Disable the Two Wire Interface module</td>
344 </tr>
345 <tr>
346 <td>\c power_usart_enable()</td>
347 <td>Enable the USART module</td>
348 </tr>
349 <tr>
350 <td>\c power_usart_disable()</td>
351 <td>Disable the USART module</td>
352 </tr>
353 <tr>
354 <td>\c power_usart0_enable()</td>
355 <td>Enable the USART 0 module</td>
356 </tr>
357 <tr>
358 <td>\c power_usart0_disable()</td>
359 <td>Disable the USART 0 module</td>
360 </tr>
361 <tr>
362 <td>\c power_usart1_enable()</td>
363 <td>Enable the USART 1 module</td>
364 </tr>
365 <tr>
366 <td>\c power_usart1_disable()</td>
367 <td>Disable the USART 1 module</td>
368 </tr>
369 <tr>
370 <td>\c power_usart2_enable()</td>
371 <td>Enable the USART 2 module</td>
372 </tr>
373 <tr>
374 <td>\c power_usart2_disable()</td>
375 <td>Disable the USART 2 module</td>
376 </tr>
377 <tr>
378 <td>\c power_usart3_enable()</td>
379 <td>Enable the USART 3 module</td>
380 </tr>
381 <tr>
382 <td>\c power_usart3_disable()</td>
383 <td>Disable the USART 3 module</td>
384 </tr>
385 <tr>
386 <td>\c power_usartc0_disable()</td>
387 <td> Disable the USART0 module on PortC</td>
388 </tr>
389 <tr>
390 <td>\c power_usartc0_enable()</td>
391 <td> Enable the USART0 module on PortC</td>
392 </tr>
393 <tr>
394 <td>\c power_usartd0_disable()</td>
395 <td> Disable the USART0 module on PortD</td>
396 </tr>
397 <tr>
398 <td>\c power_usartd0_enable()</td>
399 <td> Enable the USART0 module on PortD</td>
400 </tr>
401 <tr>
402 <td>\c power_usarte0_disable()</td>
403 <td> Disable the USART0 module on PortE</td>
404 </tr>
405 <tr>
406 <td>\c power_usarte0_enable()</td>
407 <td> Enable the USART0 module on PortE</td>
408 </tr>
409 <tr>
410 <td>\c power_usartf0_disable()</td>
411 <td> Disable the USART0 module on PortF</td>
412 </tr>
413 <tr>
414 <td>\c power_usartf0_enable()</td>
415 <td> Enable the USART0 module on PortF</td>
416 </tr>
417 <tr>
418 <td>\c power_usb_enable()</td>
419 <td>Enable the USB module</td>
420 </tr>
421 <tr>
422 <td>\c power_usb_disable()</td>
423 <td>Disable the USB module</td>
424 </tr>
425 <tr>
426 <td>\c power_usi_enable()</td>
427 <td>Enable the Universal Serial Interface module</td>
428 </tr>
429 <tr>
430 <td>\c power_usi_disable()</td>
431 <td>Disable the Universal Serial Interface module</td>
432 </tr>
433 <tr>
434 <td>\c power_vadc_enable()</td>
435 <td>Enable the Voltage ADC module</td>
436 </tr>
437 <tr>
438 <td>\c power_vadc_disable()</td>
439 <td>Disable the Voltage ADC module</td>
440 </tr>
441 <tr>
442 <td>\c power_all_enable()</td>
443 <td>Enable all modules</td>
444 </tr>
445 <tr>
446 <td>\c power_all_disable()</td>
447 <td>Disable all modules</td>
448 </tr>
449</table>
450</small>
451*/
452
453#if defined(__AVR_HAVE_PRR_PRADC)
454#define power_adc_enable() (PRR &= (uint8_t)~(1 << PRADC))
455#define power_adc_disable() (PRR |= (uint8_t)(1 << PRADC))
456#endif
457
458#if defined(__AVR_HAVE_PRR_PRCAN)
459#define power_can_enable() (PRR &= (uint8_t)~(1 << PRCAN))
460#define power_can_disable() (PRR |= (uint8_t)(1 << PRCAN))
461#endif
462
463#if defined(__AVR_HAVE_PRR_PRLCD)
464#define power_lcd_enable() (PRR &= (uint8_t)~(1 << PRLCD))
465#define power_lcd_disable() (PRR |= (uint8_t)(1 << PRLCD))
466#endif
467
468#if defined(__AVR_HAVE_PRR_PRLIN)
469#define power_lin_enable() (PRR &= (uint8_t)~(1 << PRLIN))
470#define power_lin_disable() (PRR |= (uint8_t)(1 << PRLIN))
471#endif
472
473#if defined(__AVR_HAVE_PRR_PRPSC)
474#define power_psc_enable() (PRR &= (uint8_t)~(1 << PRPSC))
475#define power_psc_disable() (PRR |= (uint8_t)(1 << PRPSC))
476#endif
477
478#if defined(__AVR_HAVE_PRR_PRPSC0)
479#define power_psc0_enable() (PRR &= (uint8_t)~(1 << PRPSC0))
480#define power_psc0_disable() (PRR |= (uint8_t)(1 << PRPSC0))
481#endif
482
483#if defined(__AVR_HAVE_PRR_PRPSC1)
484#define power_psc1_enable() (PRR &= (uint8_t)~(1 << PRPSC1))
485#define power_psc1_disable() (PRR |= (uint8_t)(1 << PRPSC1))
486#endif
487
488#if defined(__AVR_HAVE_PRR_PRPSC2)
489#define power_psc2_enable() (PRR &= (uint8_t)~(1 << PRPSC2))
490#define power_psc2_disable() (PRR |= (uint8_t)(1 << PRPSC2))
491#endif
492
493#if defined(__AVR_HAVE_PRR_PRPSCR)
494#define power_pscr_enable() (PRR &= (uint8_t)~(1 << PRPSCR))
495#define power_pscr_disable() (PRR |= (uint8_t)(1 << PRPSCR))
496#endif
497
498#if defined(__AVR_HAVE_PRR_PRSPI)
499#define power_spi_enable() (PRR &= (uint8_t)~(1 << PRSPI))
500#define power_spi_disable() (PRR |= (uint8_t)(1 << PRSPI))
501#endif
502
503#if defined(__AVR_HAVE_PRR_PRTIM0)
504#define power_timer0_enable() (PRR &= (uint8_t)~(1 << PRTIM0))
505#define power_timer0_disable() (PRR |= (uint8_t)(1 << PRTIM0))
506#endif
507
508#if defined(__AVR_HAVE_PRR_PRTIM1)
509#define power_timer1_enable() (PRR &= (uint8_t)~(1 << PRTIM1))
510#define power_timer1_disable() (PRR |= (uint8_t)(1 << PRTIM1))
511#endif
512
513#if defined(__AVR_HAVE_PRR_PRTIM2)
514#define power_timer2_enable() (PRR &= (uint8_t)~(1 << PRTIM2))
515#define power_timer2_disable() (PRR |= (uint8_t)(1 << PRTIM2))
516#endif
517
518#if defined(__AVR_HAVE_PRR_PRTWI)
519#define power_twi_enable() (PRR &= (uint8_t)~(1 << PRTWI))
520#define power_twi_disable() (PRR |= (uint8_t)(1 << PRTWI))
521#endif
522
523#if defined(__AVR_HAVE_PRR_PRUSART)
524#define power_usart_enable() (PRR &= (uint8_t)~(1 << PRUSART))
525#define power_usart_disable() (PRR |= (uint8_t)(1 << PRUSART))
526#endif
527
528#if defined(__AVR_HAVE_PRR_PRUSART0)
529#define power_usart0_enable() (PRR &= (uint8_t)~(1 << PRUSART0))
530#define power_usart0_disable() (PRR |= (uint8_t)(1 << PRUSART0))
531#endif
532
533#if defined(__AVR_HAVE_PRR_PRUSART1)
534#define power_usart1_enable() (PRR &= (uint8_t)~(1 << PRUSART1))
535#define power_usart1_disable() (PRR |= (uint8_t)(1 << PRUSART1))
536#endif
537
538#if defined(__AVR_HAVE_PRR_PRUSI)
539#define power_usi_enable() (PRR &= (uint8_t)~(1 << PRUSI))
540#define power_usi_disable() (PRR |= (uint8_t)(1 << PRUSI))
541#endif
542
543#if defined(__AVR_HAVE_PRR0_PRADC)
544#define power_adc_enable() (PRR0 &= (uint8_t)~(1 << PRADC))
545#define power_adc_disable() (PRR0 |= (uint8_t)(1 << PRADC))
546#endif
547
548#if defined(__AVR_HAVE_PRR0_PRC0)
549#define power_clock_output_enable() (PRR0 &= (uint8_t)~(1 << PRCO))
550#define power_clock_output_disable() (PRR0 |= (uint8_t)(1 << PRCO))
551#endif
552
553#if defined(__AVR_HAVE_PRR0_PRCRC)
554#define power_crc_enable() (PRR0 &= (uint8_t)~(1 << PRCRC))
555#define power_crc_disable() (PRR0 |= (uint8_t)(1 << PRCRC))
556#endif
557
558#if defined(__AVR_HAVE_PRR0_PRCU)
559#define power_crypto_enable() (PRR0 &= (uint8_t)~(1 << PRCU))
560#define power_crypto_disable() (PRR0 |= (uint8_t)(1 << PRCU))
561#endif
562
563#if defined(__AVR_HAVE_PRR0_PRDS)
564#define power_irdriver_enable() (PRR0 &= (uint8_t)~(1 << PRDS))
565#define power_irdriver_disable() (PRR0 |= (uint8_t)(1 << PRDS))
566#endif
567
568#if defined(__AVR_HAVE_PRR0_PRLFR)
569#define power_lfreceiver_enable() (PRR0 &= (uint8_t)~(1 << PRLFR))
570#define power_lfreceiver_disable() (PRR0 |= (uint8_t)(1 << PRLFR))
571#endif
572
573#if defined(__AVR_HAVE_PRR0_PRLFRS)
574#define power_lfrs_enable() (PRR0 &= (uint8_t)~(1 << PRLFRS))
575#define power_lfrs_disable() (PRR0 |= (uint8_t)(1 << PRLFRS))
576#endif
577
578#if defined(__AVR_HAVE_PRR0_PRLIN)
579#define power_lin_enable() (PRR0 &= (uint8_t)~(1 << PRLIN))
580#define power_lin_disable() (PRR0 |= (uint8_t)(1 << PRLIN))
581#endif
582
583#if defined(__AVR_HAVE_PRR0_PRPGA)
584#define power_pga_enable() (PRR0 &= (uint8_t)~(1 << PRPGA))
585#define power_pga_disable() (PRR0 |= (uint8_t)(1 << PRPGA))
586#endif
587
588#if defined(__AVR_HAVE_PRR0_PRRXDC)
589#define power_receive_dsp_control_enable() (PRR0 &= (uint8_t)~(1 << PRRXDC))
590#define power_receive_dsp_control_disable() (PRR0 |= (uint8_t)(1 << PRRXDC))
591#endif
592
593#if defined(__AVR_HAVE_PRR0_PRSPI)
594#define power_spi_enable() (PRR0 &= (uint8_t)~(1 << PRSPI))
595#define power_spi_disable() (PRR0 |= (uint8_t)(1 << PRSPI))
596#endif
597
598#if defined(__AVR_HAVE_PRR0_PRT0)
599#define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRT0))
600#define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRT0))
601#endif
602
603#if defined(__AVR_HAVE_PRR0_PRTIM0)
604#define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRTIM0))
605#define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRTIM0))
606#endif
607
608#if defined(__AVR_HAVE_PRR0_PRT1)
609#define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRT1))
610#define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRT1))
611#endif
612
613#if defined(__AVR_HAVE_PRR0_PRTIM1)
614#define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRTIM1))
615#define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRTIM1))
616#endif
617
618#if defined(__AVR_HAVE_PRR0_PRT2)
619#define power_timer2_enable() (PRR0 &= (uint8_t)~(1 << PRT2))
620#define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRT2))
621#endif
622
623#if defined(__AVR_HAVE_PRR0_PRTIM2)
624#define power_timer2_enable() (PRR0 &= (uint8_t)~(1 << PRTIM2))
625#define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRTIM2))
626#endif
627
628#if defined(__AVR_HAVE_PRR0_PRT3)
629#define power_timer3_enable() (PRR0 &= (uint8_t)~(1 << PRT3))
630#define power_timer3_disable() (PRR0 |= (uint8_t)(1 << PRT3))
631#endif
632
633#if defined(__AVR_HAVE_PRR0_PRTM)
634#define power_timermodulator_enable() (PRR0 &= (uint8_t)~(1 << PRTM))
635#define power_timermodulator_disable() (PRR0 |= (uint8_t)(1 << PRTM))
636#endif
637
638#if defined(__AVR_HAVE_PRR0_PRTWI)
639#define power_twi_enable() (PRR0 &= (uint8_t)~(1 << PRTWI))
640#define power_twi_disable() (PRR0 |= (uint8_t)(1 << PRTWI))
641#endif
642
643#if defined(__AVR_HAVE_PRR0_PRTWI1)
644#define power_twi1_enable() (PRR0 &= (uint8_t)~(1 << PRTWI1))
645#define power_twi1_disable() (PRR0 |= (uint8_t)(1 << PRTWI1))
646#endif
647
648#if defined(__AVR_HAVE_PRR0_PRTXDC)
649#define power_transmit_dsp_control_enable() (PRR0 &= (uint8_t)~(1 << PRTXDC))
650#define power_transmit_dsp_control_disable() (PRR0 |= (uint8_t)(1 << PRTXDC))
651#endif
652
653#if defined(__AVR_HAVE_PRR0_PRUSART0)
654#define power_usart0_enable() (PRR0 &= (uint8_t)~(1 << PRUSART0))
655#define power_usart0_disable() (PRR0 |= (uint8_t)(1 << PRUSART0))
656#endif
657
658#if defined(__AVR_HAVE_PRR0_PRUSART1)
659#define power_usart1_enable() (PRR0 &= (uint8_t)~(1 << PRUSART1))
660#define power_usart1_disable() (PRR0 |= (uint8_t)(1 << PRUSART1))
661#endif
662
663#if defined(__AVR_HAVE_PRR0_PRVADC)
664#define power_vadc_enable() (PRR0 &= (uint8_t)~(1 << PRVADC))
665#define power_vadc_disable() (PRR0 |= (uint8_t)(1 << PRVADC))
666#endif
667
668#if defined(__AVR_HAVE_PRR0_PRVM)
669#define power_voltage_monitor_enable() (PRR0 &= (uint8_t)~(1 << PRVM))
670#define power_voltage_monitor_disable() (PRR0 |= (uint8_t)(1 << PRVM))
671#endif
672
673#if defined(__AVR_HAVE_PRR0_PRVRM)
674#define power_vrm_enable() (PRR0 &= (uint8_t)~(1 << PRVRM))
675#define power_vrm_disable() (PRR0 |= (uint8_t)(1 << PRVRM))
676#endif
677
678#if defined(__AVR_HAVE_PRR1_PRAES)
679#define power_aes_enable() (PRR1 &= (uint8_t)~(1 << PRAES))
680#define power_aes_disable() (PRR1 |= (uint8_t)(1 << PRAES))
681#endif
682
683#if defined(__AVR_HAVE_PRR1_PRCI)
684#define power_cinterface_enable() (PRR1 &= (uint8_t)~(1 << PRCI))
685#define power_cinterface_disable() (PRR1 |= (uint8_t)(1 << PRCI))
686#endif
687
688#if defined(__AVR_HAVE_PRR1_PRHSSPI)
689#define power_hsspi_enable() (PRR1 &= (uint8_t)~(1 << PRHSSPI))
690#define power_hsspi_disable() (PRR1 |= (uint8_t)(1 << PRHSSPI))
691#endif
692
693#if defined(__AVR_HAVE_PRR1_PRKB)
694#define power_kb_enable() (PRR1 &= (uint8_t)~(1 << PRKB))
695#define power_kb_disable() (PRR1 |= (uint8_t)(1 << PRKB))
696#endif
697
698#if defined(__AVR_HAVE_PRR1_PRLFPH)
699#define power_lfph_enable() (PRR1 &= (uint8_t)~(1 << PRLFPH))
700#define power_lfph_disable() (PRR1 |= (uint8_t)(1 << PRLFPH))
701#endif
702
703#if defined(__AVR_HAVE_PRR1_PRLFR)
704#define power_lfreceiver_enable() (PRR1 &= (uint8_t)~(1 << PRLFR))
705#define power_lfreceiver_disable() (PRR1 |= (uint8_t)(1 << PRLFR))
706#endif
707
708#if defined(__AVR_HAVE_PRR1_PRLFTP)
709#define power_lftp_enable() (PRR1 &= (uint8_t)~(1 << PRLFTP))
710#define power_lftp_disable() (PRR1 |= (uint8_t)(1 << PRLFTP))
711#endif
712
713#if defined(__AVR_HAVE_PRR1_PRSCI)
714#define power_sci_enable() (PRR1 &= (uint8_t)~(1 << PRSCI))
715#define power_sci_disable() (PRR1 |= (uint8_t)(1 << PRSCI))
716#endif
717
718#if defined(__AVR_HAVE_PRR1_PRSPI)
719#define power_spi_enable() (PRR1 &= (uint8_t)~(1 << PRSPI))
720#define power_spi_disable() (PRR1 |= (uint8_t)(1 << PRSPI))
721#endif
722
723#if defined(__AVR_HAVE_PRR1_PRT1)
724#define power_timer1_enable() (PRR1 &= (uint8_t)~(1 << PRT1))
725#define power_timer1_disable() (PRR1 |= (uint8_t)(1 << PRT1))
726#endif
727
728#if defined(__AVR_HAVE_PRR1_PRT2)
729#define power_timer2_enable() (PRR1 &= (uint8_t)~(1 << PRT2))
730#define power_timer2_disable() (PRR1 |= (uint8_t)(1 << PRT2))
731#endif
732
733#if defined(__AVR_HAVE_PRR1_PRT3)
734#define power_timer3_enable() (PRR1 &= (uint8_t)~(1 << PRT3))
735#define power_timer3_disable() (PRR1 |= (uint8_t)(1 << PRT3))
736#endif
737
738#if defined(__AVR_HAVE_PRR1_PRT4)
739#define power_timer4_enable() (PRR1 &= (uint8_t)~(1 << PRT4))
740#define power_timer4_disable() (PRR1 |= (uint8_t)(1 << PRT4))
741#endif
742
743#if defined(__AVR_HAVE_PRR1_PRT5)
744#define power_timer5_enable() (PRR1 &= (uint8_t)~(1 << PRT5))
745#define power_timer5_disable() (PRR1 |= (uint8_t)(1 << PRT5))
746#endif
747
748#if defined(__AVR_HAVE_PRR1_PRTIM3)
749#define power_timer3_enable() (PRR1 &= (uint8_t)~(1 << PRTIM3))
750#define power_timer3_disable() (PRR1 |= (uint8_t)(1 << PRTIM3))
751#endif
752
753#if defined(__AVR_HAVE_PRR1_PRTIM4)
754#define power_timer4_enable() (PRR1 &= (uint8_t)~(1 << PRTIM4))
755#define power_timer4_disable() (PRR1 |= (uint8_t)(1 << PRTIM4))
756#endif
757
758#if defined(__AVR_HAVE_PRR1_PRTIM5)
759#define power_timer5_enable() (PRR1 &= (uint8_t)~(1 << PRTIM5))
760#define power_timer5_disable() (PRR1 |= (uint8_t)(1 << PRTIM5))
761#endif
762
763#if defined(__AVR_HAVE_PRR1_PRTRX24)
764#define power_transceiver_enable() (PRR1 &= (uint8_t)~(1 << PRTRX24))
765#define power_transceiver_disable() (PRR1 |= (uint8_t)(1 << PRTRX24))
766#endif
767
768#if defined(__AVR_HAVE_PRR1_PRUSART1)
769#define power_usart1_enable() (PRR1 &= (uint8_t)~(1 << PRUSART1))
770#define power_usart1_disable() (PRR1 |= (uint8_t)(1 << PRUSART1))
771#endif
772
773#if defined(__AVR_HAVE_PRR1_PRUSART2)
774#define power_usart2_enable() (PRR1 &= (uint8_t)~(1 << PRUSART2))
775#define power_usart2_disable() (PRR1 |= (uint8_t)(1 << PRUSART2))
776#endif
777
778#if defined(__AVR_HAVE_PRR1_PRUSART3)
779#define power_usart3_enable() (PRR1 &= (uint8_t)~(1 << PRUSART3))
780#define power_usart3_disable() (PRR1 |= (uint8_t)(1 << PRUSART3))
781#endif
782
783#if defined(__AVR_HAVE_PRR1_PRUSB)
784#define power_usb_enable() (PRR1 &= (uint8_t)~(1 << PRUSB))
785#define power_usb_disable() (PRR1 |= (uint8_t)(1 << PRUSB))
786#endif
787
788#if defined(__AVR_HAVE_PRR1_PRUSBH)
789#define power_usbh_enable() (PRR1 &= (uint8_t)~(1 << PRUSBH))
790#define power_usbh_disable() (PRR1 |= (uint8_t)(1 << PRUSBH))
791#endif
792
793#if defined(__AVR_HAVE_PRR2_PRDF)
794#define power_data_fifo_enable() (PRR2 &= (uint8_t)~(1 << PRDF))
795#define power_data_fifo_disable() (PRR2 |= (uint8_t)(1 << PRDF))
796#endif
797
798#if defined(__AVR_HAVE_PRR2_PRIDS)
799#define power_id_scan_enable() (PRR2 &= (uint8_t)~(1 << PRIDS))
800#define power_id_scan_disable() (PRR2 |= (uint8_t)(1 << PRIDS))
801#endif
802
803#if defined(__AVR_HAVE_PRR2_PRRAM0)
804#define power_ram0_enable() (PRR2 &= (uint8_t)~(1 << PRRAM0))
805#define power_ram0_disable() (PRR2 |= (uint8_t)(1 << PRRAM0))
806#endif
807
808#if defined(__AVR_HAVE_PRR2_PRRAM1)
809#define power_ram1_enable() (PRR2 &= (uint8_t)~(1 << PRRAM1))
810#define power_ram1_disable() (PRR2 |= (uint8_t)(1 << PRRAM1))
811#endif
812
813#if defined(__AVR_HAVE_PRR2_PRRAM2)
814#define power_ram2_enable() (PRR2 &= (uint8_t)~(1 << PRRAM2))
815#define power_ram2_disable() (PRR2 |= (uint8_t)(1 << PRRAM2))
816#endif
817
818#if defined(__AVR_HAVE_PRR2_PRRAM3)
819#define power_ram3_enable() (PRR2 &= (uint8_t)~(1 << PRRAM3))
820#define power_ram3_disable() (PRR2 |= (uint8_t)(1 << PRRAM3))
821#endif
822
823#if defined(__AVR_HAVE_PRR2_PRRS)
824#define power_rssi_buffer_enable() (PRR2 &= (uint8_t)~(1 << PRRS))
825#define power_rssi_buffer_disable() (PRR2 |= (uint8_t)(1 << PRRS))
826#endif
827
828#if defined(__AVR_HAVE_PRR2_PRSF)
829#define power_preamble_rssi_fifo_enable() (PRR2 &= (uint8_t)~(1 << PRSF))
830#define power_preamble_rssi_fifo_disable() (PRR2 |= (uint8_t)(1 << PRSF))
831#endif
832
833#if defined(__AVR_HAVE_PRR2_PRSPI2)
834#define power_spi2_enable() (PRR2 &= (uint8_t)~(1 << PRSPI2))
835#define power_spi2_disable() (PRR2 |= (uint8_t)(1 << PRSPI2))
836#endif
837
838#if defined(__AVR_HAVE_PRR2_PRSSM)
839#define power_sequencer_state_machine_enable() (PRR2 &= (uint8_t)~(1 << PRSSM))
840#define power_sequencer_state_machine_disable() (PRR2 |= (uint8_t)(1 << PRSSM))
841#endif
842
843#if defined(__AVR_HAVE_PRR2_PRTM)
844#define power_tx_modulator_enable() (PRR2 &= (uint8_t)~(1 << PRTM))
845#define power_tx_modulator_disable() (PRR2 |= (uint8_t)(1 << PRTM))
846#endif
847
848#if defined(__AVR_HAVE_PRR2_PRTWI2)
849#define power_twi2_enable() (PRR2 &= (uint8_t)~(1 << PRTWI2))
850#define power_twi2_disable() (PRR2 |= (uint8_t)(1 << PRTWI2))
851#endif
852
853#if defined(__AVR_HAVE_PRR2_PRXA)
854#define power_rx_buffer_A_enable() (PRR2 &= (uint8_t)~(1 << PRXA))
855#define power_rx_buffer_A_disable() (PRR2 |= (uint8_t)(1 << PRXA))
856#endif
857
858#if defined(__AVR_HAVE_PRR2_PRXB)
859#define power_rx_buffer_B_enable() (PRR2 &= (uint8_t)~(1 << PRXB))
860#define power_rx_buffer_B_disable() (PRR2 |= (uint8_t)(1 << PRXB))
861#endif
862
863#if defined(__AVR_HAVE_PRGEN_AES)
864#define power_aes_enable() (PR_PRGEN &= (uint8_t)~(PR_AES_bm))
865#define power_aes_disable() (PR_PRGEN |= (uint8_t)PR_AES_bm)
866#endif
867
868#if defined(__AVR_HAVE_PRGEN_DMA)
869#define power_dma_enable() (PR_PRGEN &= (uint8_t)~(PR_DMA_bm))
870#define power_dma_disable() (PR_PRGEN |= (uint8_t)PR_DMA_bm)
871#endif
872
873#if defined(__AVR_HAVE_PRGEN_EBI)
874#define power_ebi_enable() (PR_PRGEN &= (uint8_t)~(PR_EBI_bm))
875#define power_ebi_disable() (PR_PRGEN |= (uint8_t)PR_EBI_bm)
876#endif
877
878#if defined(__AVR_HAVE_PRGEN_EDMA)
879#define power_edma_enable() (PR_PRGEN &= (uint8_t)~(PR_EDMA_bm))
880#define power_edma_disable() (PR_PRGEN |= (uint8_t)PR_EDMA_bm)
881#endif
882
883#if defined(__AVR_HAVE_PRGEN_EVSYS)
884#define power_evsys_enable() (PR_PRGEN &= (uint8_t)~(PR_EVSYS_bm))
885#define power_evsys_disable() (PR_PRGEN |= (uint8_t)PR_EVSYS_bm)
886#endif
887
888#if defined(__AVR_HAVE_PRGEN_LCD)
889#define power_lcd_enable() (PR_PRGEN &= (uint8_t)~(PR_LCD_bm))
890#define power_lcd_disable() (PR_PRGEN |= (uint8_t)PR_LCD_bm)
891#endif
892
893#if defined(__AVR_HAVE_PRGEN_RTC)
894#define power_rtc_enable() (PR_PRGEN &= (uint8_t)~(PR_RTC_bm))
895#define power_rtc_disable() (PR_PRGEN |= (uint8_t)PR_RTC_bm)
896#endif
897
898#if defined(__AVR_HAVE_PRGEN_USB)
899#define power_usb_enable() (PR_PRGEN &= (uint8_t)~(PR_USB_bm))
900#define power_usb_disable() (PR_PRGEN &= (uint8_t)(PR_USB_bm))
901#endif
902
903#if defined(__AVR_HAVE_PRGEN_XCL)
904#define power_xcl_enable() (PR_PRGEN &= (uint8_t)~(PR_XCL_bm))
905#define power_xcl_disable() (PR_PRGEN |= (uint8_t)PR_XCL_bm)
906#endif
907
908#if defined(__AVR_HAVE_PRPA_AC)
909#define power_aca_enable() (PR_PRPA &= (uint8_t)~(PR_AC_bm))
910#define power_aca_disable() (PR_PRPA |= (uint8_t)PR_AC_bm)
911#endif
912
913#if defined(__AVR_HAVE_PRPA_ADC)
914#define power_adca_enable() (PR_PRPA &= (uint8_t)~(PR_ADC_bm))
915#define power_adca_disable() (PR_PRPA |= (uint8_t)PR_ADC_bm)
916#endif
917
918#if defined(__AVR_HAVE_PRPA_DAC)
919#define power_daca_enable() (PR_PRPA &= (uint8_t)~(PR_DAC_bm))
920#define power_daca_disable() (PR_PRPA |= (uint8_t)PR_DAC_bm)
921#endif
922
923#if defined(__AVR_HAVE_PRPB_AC)
924#define power_acb_enable() (PR_PRPB &= (uint8_t)~(PR_AC_bm))
925#define power_acb_disable() (PR_PRPB |= (uint8_t)PR_AC_bm)
926#endif
927
928#if defined(__AVR_HAVE_PRPB_ADC)
929#define power_adcb_enable() (PR_PRPB &= (uint8_t)~(PR_ADC_bm))
930#define power_adcb_disable() (PR_PRPB |= (uint8_t)PR_ADC_bm)
931#endif
932
933#if defined(__AVR_HAVE_PRPB_DAC)
934#define power_dacb_enable() (PR_PRPB &= (uint8_t)~(PR_DAC_bm))
935#define power_dacb_disable() (PR_PRPB |= (uint8_t)PR_DAC_bm)
936#endif
937
938#if defined(__AVR_HAVE_PRPC_HIRES)
939#define power_hiresc_enable() (PR_PRPC &= (uint8_t)~(PR_HIRES_bm))
940#define power_hiresc_disable() (PR_PRPC |= (uint8_t)PR_HIRES_bm)
941#endif
942
943#if defined(__AVR_HAVE_PRPC_SPI)
944#define power_spic_enable() (PR_PRPC &= (uint8_t)~(PR_SPI_bm))
945#define power_spic_disable() (PR_PRPC |= (uint8_t)PR_SPI_bm)
946#endif
947
948#if defined(__AVR_HAVE_PRPC_TC0)
949#define power_tc0c_enable() (PR_PRPC &= (uint8_t)~(PR_TC0_bm))
950#define power_tc0c_disable() (PR_PRPC |= (uint8_t)PR_TC0_bm)
951#endif
952
953#if defined(__AVR_HAVE_PRPC_TC1)
954#define power_tc1c_enable() (PR_PRPC &= (uint8_t)~(PR_TC1_bm))
955#define power_tc1c_disable() (PR_PRPC |= (uint8_t)PR_TC1_bm)
956#endif
957
958#if defined(__AVR_HAVE_PRPC_TC4)
959#define power_tc4c_enable() (PR_PRPC &= (uint8_t)~(PR_TC4_bm))
960#define power_tc4c_disable() (PR_PRPC |= (uint8_t)PR_TC4_bm)
961#endif
962
963#if defined(__AVR_HAVE_PRPC_TC5)
964#define power_tc5c_enable() (PR_PRPC &= (uint8_t)~(PR_TC5_bm))
965#define power_tc5c_disable() (PR_PRPC |= (uint8_t)PR_TC5_bm)
966#endif
967
968#if defined(__AVR_HAVE_PRPC_TWI)
969#define power_twic_enable() (PR_PRPC &= (uint8_t)~(PR_TWI_bm))
970#define power_twic_disable() (PR_PRPC |= (uint8_t)PR_TWI_bm)
971#endif
972
973#if defined(__AVR_HAVE_PRPC_USART0)
974#define power_usartc0_enable() (PR_PRPC &= (uint8_t)~(PR_USART0_bm))
975#define power_usartc0_disable() (PR_PRPC |= (uint8_t)PR_USART0_bm)
976#endif
977
978#if defined(__AVR_HAVE_PRPC_USART1)
979#define power_usartc1_enable() (PR_PRPC &= (uint8_t)~(PR_USART1_bm))
980#define power_usartc1_disable() (PR_PRPC |= (uint8_t)PR_USART1_bm)
981#endif
982
983#if defined(__AVR_HAVE_PRPD_HIRES)
984#define power_hiresd_enable() (PR_PRPD &= (uint8_t)~(PR_HIRES_bm))
985#define power_hiresd_disable() (PR_PRPD |= (uint8_t)PR_HIRES_bm)
986#endif
987
988#if defined(__AVR_HAVE_PRPD_SPI)
989#define power_spid_enable() (PR_PRPD &= (uint8_t)~(PR_SPI_bm))
990#define power_spid_disable() (PR_PRPD |= (uint8_t)PR_SPI_bm)
991#endif
992
993#if defined(__AVR_HAVE_PRPD_TC0)
994#define power_tc0d_enable() (PR_PRPD &= (uint8_t)~(PR_TC0_bm))
995#define power_tc0d_disable() (PR_PRPD |= (uint8_t)PR_TC0_bm)
996#endif
997
998#if defined(__AVR_HAVE_PRPD_TC1)
999#define power_tc1d_enable() (PR_PRPD &= (uint8_t)~(PR_TC1_bm))
1000#define power_tc1d_disable() (PR_PRPD |= (uint8_t)PR_TC1_bm)
1001#endif
1002
1003#if defined(__AVR_HAVE_PRPD_TC5)
1004#define power_tc5d_enable() (PR_PRPD &= (uint8_t)~(PR_TC5_bm))
1005#define power_tc5d_disable() (PR_PRPD |= (uint8_t)PR_TC5_bm)
1006#endif
1007
1008#if defined(__AVR_HAVE_PRPD_TWI)
1009#define power_twid_enable() (PR_PRPD &= (uint8_t)~(PR_TWI_bm))
1010#define power_twid_disable() (PR_PRPD |= (uint8_t)PR_TWI_bm)
1011#endif
1012
1013#if defined(__AVR_HAVE_PRPD_USART0)
1014#define power_usartd0_enable() (PR_PRPD &= (uint8_t)~(PR_USART0_bm))
1015#define power_usartd0_disable() (PR_PRPD |= (uint8_t)PR_USART0_bm)
1016#endif
1017
1018#if defined(__AVR_HAVE_PRPD_USART1)
1019#define power_usartd1_enable() (PR_PRPD &= (uint8_t)~(PR_USART1_bm))
1020#define power_usartd1_disable() (PR_PRPD |= (uint8_t)PR_USART1_bm)
1021#endif
1022
1023#if defined(__AVR_HAVE_PRPE_HIRES)
1024#define power_hirese_enable() (PR_PRPE &= (uint8_t)~(PR_HIRES_bm))
1025#define power_hirese_disable() (PR_PRPE |= (uint8_t)PR_HIRES_bm)
1026#endif
1027
1028#if defined(__AVR_HAVE_PRPE_SPI)
1029#define power_spie_enable() (PR_PRPE &= (uint8_t)~(PR_SPI_bm))
1030#define power_spie_disable() (PR_PRPE |= (uint8_t)PR_SPI_bm)
1031#endif
1032
1033#if defined(__AVR_HAVE_PRPE_TC0)
1034#define power_tc0e_enable() (PR_PRPE &= (uint8_t)~(PR_TC0_bm))
1035#define power_tc0e_disable() (PR_PRPE |= (uint8_t)PR_TC0_bm)
1036#endif
1037
1038#if defined(__AVR_HAVE_PRPE_TC1)
1039#define power_tc1e_enable() (PR_PRPE &= (uint8_t)~(PR_TC1_bm))
1040#define power_tc1e_disable() (PR_PRPE |= (uint8_t)PR_TC1_bm)
1041#endif
1042
1043#if defined(__AVR_HAVE_PRPE_TWI)
1044#define power_twie_enable() (PR_PRPE &= (uint8_t)~(PR_TWI_bm))
1045#define power_twie_disable() (PR_PRPE |= (uint8_t)PR_TWI_bm)
1046#endif
1047
1048#if defined(__AVR_HAVE_PRPE_USART0)
1049#define power_usarte0_enable() (PR_PRPE &= (uint8_t)~(PR_USART0_bm))
1050#define power_usarte0_disable() (PR_PRPE |= (uint8_t)PR_USART0_bm)
1051#endif
1052
1053#if defined(__AVR_HAVE_PRPE_USART1)
1054#define power_usarte1_enable() (PR_PRPE &= (uint8_t)~(PR_USART1_bm))
1055#define power_usarte1_disable() (PR_PRPE |= (uint8_t)PR_USART1_bm)
1056#endif
1057
1058#if defined(__AVR_HAVE_PRPF_HIRES)
1059#define power_hiresf_enable() (PR_PRPF &= (uint8_t)~(PR_HIRES_bm))
1060#define power_hiresf_disable() (PR_PRPF |= (uint8_t)PR_HIRES_bm)
1061#endif
1062
1063#if defined(__AVR_HAVE_PRPF_SPI)
1064#define power_spif_enable() (PR_PRPF &= (uint8_t)~(PR_SPI_bm))
1065#define power_spif_disable() (PR_PRPF |= (uint8_t)PR_SPI_bm)
1066#endif
1067
1068#if defined(__AVR_HAVE_PRPF_TC0)
1069#define power_tc0f_enable() (PR_PRPF &= (uint8_t)~(PR_TC0_bm))
1070#define power_tc0f_disable() (PR_PRPF |= (uint8_t)PR_TC0_bm)
1071#endif
1072
1073#if defined(__AVR_HAVE_PRPF_TC1)
1074#define power_tc1f_enable() (PR_PRPF &= (uint8_t)~(PR_TC1_bm))
1075#define power_tc1f_disable() (PR_PRPF |= (uint8_t)PR_TC1_bm)
1076#endif
1077
1078#if defined(__AVR_HAVE_PRPF_TWI)
1079#define power_twif_enable() (PR_PRPF &= (uint8_t)~(PR_TWI_bm))
1080#define power_twif_disable() (PR_PRPF |= (uint8_t)PR_TWI_bm)
1081#endif
1082
1083#if defined(__AVR_HAVE_PRPF_USART0)
1084#define power_usartf0_enable() (PR_PRPF &= (uint8_t)~(PR_USART0_bm))
1085#define power_usartf0_disable() (PR_PRPF |= (uint8_t)PR_USART0_bm)
1086#endif
1087
1088#if defined(__AVR_HAVE_PRPF_USART1)
1089#define power_usartf1_enable() (PR_PRPF &= (uint8_t)~(PR_USART1_bm))
1090#define power_usartf1_disable() (PR_PRPF |= (uint8_t)PR_USART1_bm)
1091#endif
1092
1093#ifdef __DOXYGEN__
1094/**
1095 \ingroup avr_power
1096 \fn void power_all_enable()
1097 Enable all modules.
1098 */
1099static __ATTR_ALWAYS_INLINE__ void power_all_enable();
1100#else
1101static __ATTR_ALWAYS_INLINE__ void __power_all_enable()
1102{
1103#ifdef __AVR_HAVE_PRR
1104 PRR &= (uint8_t)~(__AVR_HAVE_PRR);
1105#endif
1106
1107#ifdef __AVR_HAVE_PRR0
1108 PRR0 &= (uint8_t)~(__AVR_HAVE_PRR0);
1109#endif
1110
1111#ifdef __AVR_HAVE_PRR1
1112 PRR1 &= (uint8_t)~(__AVR_HAVE_PRR1);
1113#endif
1114
1115#ifdef __AVR_HAVE_PRR2
1116 PRR2 &= (uint8_t)~(__AVR_HAVE_PRR2);
1117#endif
1118
1119#ifdef __AVR_HAVE_PRGEN
1120 PR_PRGEN &= (uint8_t)~(__AVR_HAVE_PRGEN);
1121#endif
1122
1123#ifdef __AVR_HAVE_PRPA
1124 PR_PRPA &= (uint8_t)~(__AVR_HAVE_PRPA);
1125#endif
1126
1127#ifdef __AVR_HAVE_PRPB
1128 PR_PRPB &= (uint8_t)~(__AVR_HAVE_PRPB);
1129#endif
1130
1131#ifdef __AVR_HAVE_PRPC
1132 PR_PRPC &= (uint8_t)~(__AVR_HAVE_PRPC);
1133#endif
1134
1135#ifdef __AVR_HAVE_PRPD
1136 PR_PRPD &= (uint8_t)~(__AVR_HAVE_PRPD);
1137#endif
1138
1139#ifdef __AVR_HAVE_PRPE
1140 PR_PRPE &= (uint8_t)~(__AVR_HAVE_PRPE);
1141#endif
1142
1143#ifdef __AVR_HAVE_PRPF
1144 PR_PRPF &= (uint8_t)~(__AVR_HAVE_PRPF);
1145#endif
1146}
1147#endif /* __DOXYGEN__ */
1148
1149#ifdef __DOXYGEN__
1150/**
1151 \ingroup avr_power
1152 \fn void power_all_disable()
1153 Disable all modules.
1154 */
1155static __ATTR_ALWAYS_INLINE__ void power_all_disable();
1156#else
1157static __ATTR_ALWAYS_INLINE__ void __power_all_disable()
1158{
1159#ifdef __AVR_HAVE_PRR
1160 PRR |= (uint8_t)(__AVR_HAVE_PRR);
1161#endif
1162
1163#ifdef __AVR_HAVE_PRR0
1164 PRR0 |= (uint8_t)(__AVR_HAVE_PRR0);
1165#endif
1166
1167#ifdef __AVR_HAVE_PRR1
1168 PRR1 |= (uint8_t)(__AVR_HAVE_PRR1);
1169#endif
1170
1171#ifdef __AVR_HAVE_PRR2
1172 PRR2 |= (uint8_t)(__AVR_HAVE_PRR2);
1173#endif
1174
1175#ifdef __AVR_HAVE_PRGEN
1176 PR_PRGEN |= (uint8_t)(__AVR_HAVE_PRGEN);
1177#endif
1178
1179#ifdef __AVR_HAVE_PRPA
1180 PR_PRPA |= (uint8_t)(__AVR_HAVE_PRPA);
1181#endif
1182
1183#ifdef __AVR_HAVE_PRPB
1184 PR_PRPB |= (uint8_t)(__AVR_HAVE_PRPB);
1185#endif
1186
1187#ifdef __AVR_HAVE_PRPC
1188 PR_PRPC |= (uint8_t)(__AVR_HAVE_PRPC);
1189#endif
1190
1191#ifdef __AVR_HAVE_PRPD
1192 PR_PRPD |= (uint8_t)(__AVR_HAVE_PRPD);
1193#endif
1194
1195#ifdef __AVR_HAVE_PRPE
1196 PR_PRPE |= (uint8_t)(__AVR_HAVE_PRPE);
1197#endif
1198
1199#ifdef __AVR_HAVE_PRPF
1200 PR_PRPF |= (uint8_t)(__AVR_HAVE_PRPF);
1201#endif
1202}
1203#endif /* __DOXYGEN__ */
1204
1205#ifndef __DOXYGEN__
1206#ifndef power_all_enable
1207#define power_all_enable() __power_all_enable()
1208#endif
1209
1210#ifndef power_all_disable
1211#define power_all_disable() __power_all_disable()
1212#endif
1213#endif /* !__DOXYGEN__ */
1214
1215
1216#if defined(__DOXYGEN__) \
1217|| defined(__AVR_AT90CAN32__) \
1218|| defined(__AVR_AT90CAN64__) \
1219|| defined(__AVR_AT90CAN128__) \
1220|| defined(__AVR_AT90PWM1__) \
1221|| defined(__AVR_AT90PWM2__) \
1222|| defined(__AVR_AT90PWM2B__) \
1223|| defined(__AVR_AT90PWM3__) \
1224|| defined(__AVR_AT90PWM3B__) \
1225|| defined(__AVR_AT90PWM81__) \
1226|| defined(__AVR_AT90PWM161__) \
1227|| defined(__AVR_AT90PWM216__) \
1228|| defined(__AVR_AT90PWM316__) \
1229|| defined(__AVR_AT90SCR100__) \
1230|| defined(__AVR_AT90USB646__) \
1231|| defined(__AVR_AT90USB647__) \
1232|| defined(__AVR_AT90USB82__) \
1233|| defined(__AVR_AT90USB1286__) \
1234|| defined(__AVR_AT90USB1287__) \
1235|| defined(__AVR_AT90USB162__) \
1236|| defined(__AVR_ATA5505__) \
1237|| defined(__AVR_ATA5272__) \
1238|| defined(__AVR_ATmega1280__) \
1239|| defined(__AVR_ATmega1281__) \
1240|| defined(__AVR_ATmega1284__) \
1241|| defined(__AVR_ATmega128RFA1__) \
1242|| defined(__AVR_ATmega1284RFR2__) \
1243|| defined(__AVR_ATmega128RFR2__) \
1244|| defined(__AVR_ATmega1284P__) \
1245|| defined(__AVR_ATmega162__) \
1246|| defined(__AVR_ATmega164A__) \
1247|| defined(__AVR_ATmega164P__) \
1248|| defined(__AVR_ATmega164PA__) \
1249|| defined(__AVR_ATmega165__) \
1250|| defined(__AVR_ATmega165A__) \
1251|| defined(__AVR_ATmega165P__) \
1252|| defined(__AVR_ATmega165PA__) \
1253|| defined(__AVR_ATmega168__) \
1254|| defined(__AVR_ATmega168P__) \
1255|| defined(__AVR_ATmega168A__) \
1256|| defined(__AVR_ATmega168PA__) \
1257|| defined(__AVR_ATmega168PB__) \
1258|| defined(__AVR_ATmega169__) \
1259|| defined(__AVR_ATmega169A__) \
1260|| defined(__AVR_ATmega169P__) \
1261|| defined(__AVR_ATmega169PA__) \
1262|| defined(__AVR_ATmega16M1__) \
1263|| defined(__AVR_ATmega16U2__) \
1264|| defined(__AVR_ATmega16U4__) \
1265|| defined(__AVR_ATmega2560__) \
1266|| defined(__AVR_ATmega2561__) \
1267|| defined(__AVR_ATmega2564RFR2__) \
1268|| defined(__AVR_ATmega256RFR2__) \
1269|| defined(__AVR_ATmega324A__) \
1270|| defined(__AVR_ATmega324P__) \
1271|| defined(__AVR_ATmega324PA__) \
1272|| defined(__AVR_ATmega324PB__) \
1273|| defined(__AVR_ATmega325__) \
1274|| defined(__AVR_ATmega325A__) \
1275|| defined(__AVR_ATmega325PA__) \
1276|| defined(__AVR_ATmega3250__) \
1277|| defined(__AVR_ATmega3250A__) \
1278|| defined(__AVR_ATmega3250PA__) \
1279|| defined(__AVR_ATmega328__) \
1280|| defined(__AVR_ATmega328P__) \
1281|| defined(__AVR_ATmega328PB__) \
1282|| defined(__AVR_ATmega329__) \
1283|| defined(__AVR_ATmega329A__) \
1284|| defined(__AVR_ATmega329P__) \
1285|| defined(__AVR_ATmega329PA__) \
1286|| defined(__AVR_ATmega3290__) \
1287|| defined(__AVR_ATmega3290A__) \
1288|| defined(__AVR_ATmega3290P__) \
1289|| defined(__AVR_ATmega3290PA__) \
1290|| defined(__AVR_ATmega32C1__) \
1291|| defined(__AVR_ATmega32M1__) \
1292|| defined(__AVR_ATmega32U2__) \
1293|| defined(__AVR_ATmega32U4__) \
1294|| defined(__AVR_ATmega32U6__) \
1295|| defined(__AVR_ATmega48__) \
1296|| defined(__AVR_ATmega48A__) \
1297|| defined(__AVR_ATmega48PA__) \
1298|| defined(__AVR_ATmega48P__) \
1299|| defined(__AVR_ATmega640__) \
1300|| defined(__AVR_ATmega649P__) \
1301|| defined(__AVR_ATmega644__) \
1302|| defined(__AVR_ATmega644A__) \
1303|| defined(__AVR_ATmega644P__) \
1304|| defined(__AVR_ATmega644PA__) \
1305|| defined(__AVR_ATmega645__) \
1306|| defined(__AVR_ATmega645A__) \
1307|| defined(__AVR_ATmega645P__) \
1308|| defined(__AVR_ATmega6450__) \
1309|| defined(__AVR_ATmega6450A__) \
1310|| defined(__AVR_ATmega6450P__) \
1311|| defined(__AVR_ATmega649__) \
1312|| defined(__AVR_ATmega649A__) \
1313|| defined(__AVR_ATmega64M1__) \
1314|| defined(__AVR_ATmega64C1__) \
1315|| defined(__AVR_ATmega6490__) \
1316|| defined(__AVR_ATmega6490A__) \
1317|| defined(__AVR_ATmega6490P__) \
1318|| defined(__AVR_ATmega644RFR2__) \
1319|| defined(__AVR_ATmega64RFR2__) \
1320|| defined(__AVR_ATmega88__) \
1321|| defined(__AVR_ATmega88A__) \
1322|| defined(__AVR_ATmega88P__) \
1323|| defined(__AVR_ATmega88PA__) \
1324|| defined(__AVR_ATmega8U2__) \
1325|| defined(__AVR_ATmega16U2__) \
1326|| defined(__AVR_ATmega32U2__) \
1327|| defined(__AVR_ATtiny48__) \
1328|| defined(__AVR_ATtiny88__) \
1329|| defined(__AVR_ATtiny87__) \
1330|| defined(__AVR_ATtiny167__)
1331
1332
1333/** \addtogroup avr_power
1334
1335Some of the newer AVRs contain a System Clock Prescale Register (CLKPR) that
1336allows you to decrease the system clock frequency and the power consumption
1337when the need for processing power is low.
1338On some earlier AVRs (ATmega103, ATmega64, ATmega128), similar
1339functionality can be achieved through the XTAL Divide Control Register.
1340Below are two macros and an enumerated type that can be used to
1341interface to the Clock Prescale Register or
1342XTAL Divide Control Register.
1343
1344\note Not all AVR devices have a clock prescaler. On those devices
1345without a Clock Prescale Register or XTAL Divide Control Register, these
1346macros are not available.
1347
1348\code
1349typedef enum
1350{
1351 clock_div_1 = 0,
1352 clock_div_2 = 1,
1353 clock_div_4 = 2,
1354 clock_div_8 = 3,
1355 clock_div_16 = 4,
1356 clock_div_32 = 5,
1357 clock_div_64 = 6,
1358 clock_div_128 = 7,
1359 clock_div_256 = 8,
1360 clock_div_1_rc = 15, // ATmega128RFA1 only
1361} clock_div_t;
1362\endcode
1363Clock prescaler setting enumerations for device using
1364System Clock Prescale Register.
1365
1366\code
1367typedef enum
1368{
1369 clock_div_1 = 1,
1370 clock_div_2 = 2,
1371 clock_div_4 = 4,
1372 clock_div_8 = 8,
1373 clock_div_16 = 16,
1374 clock_div_32 = 32,
1375 clock_div_64 = 64,
1376 clock_div_128 = 128
1377} clock_div_t;
1378\endcode
1379Clock prescaler setting enumerations for device using
1380XTAL Divide Control Register.
1381
1382*/
1383#ifndef __DOXYGEN__
1384typedef enum
1385{
1386 clock_div_1 = 0,
1387 clock_div_2 = 1,
1388 clock_div_4 = 2,
1389 clock_div_8 = 3,
1390 clock_div_16 = 4,
1391 clock_div_32 = 5,
1392 clock_div_64 = 6,
1393 clock_div_128 = 7,
1394 clock_div_256 = 8
1395#if defined(__AVR_ATmega128RFA1__) \
1396|| defined(__AVR_ATmega2564RFR2__) \
1397|| defined(__AVR_ATmega1284RFR2__) \
1398|| defined(__AVR_ATmega644RFR2__) \
1399|| defined(__AVR_ATmega256RFR2__) \
1400|| defined(__AVR_ATmega128RFR2__) \
1401|| defined(__AVR_ATmega64RFR2__)
1402 , clock_div_1_rc = 15
1403#endif
1404} clock_div_t;
1405
1406static __ATTR_ALWAYS_INLINE__ void clock_prescale_set(clock_div_t);
1407#endif /* !__DOXYGEN__ */
1408
1409/**
1410 \ingroup avr_power
1411 \fn clock_prescale_set(clock_div_t x)
1412
1413Set the clock prescaler register select bits, selecting a system clock
1414division setting. This function is inlined, even if compiler
1415optimizations are disabled.
1416
1417The type of \c x is \c clock_div_t.
1418
1419\note For device with XTAL Divide Control Register (XDIV), \c x can actually range
1420from 1 to 129. Thus, one does not need to use \c clock_div_t type as argument.
1421*/
1422void clock_prescale_set(clock_div_t __x)
1423{
1424 uint8_t __tmp = _BV(CLKPCE);
1425 __asm__ __volatile__ (
1426 "in __tmp_reg__,__SREG__" "\n\t"
1427 "cli" "\n\t"
1428 "sts %1, %0" "\n\t"
1429 "sts %1, %2" "\n\t"
1430 "out __SREG__, __tmp_reg__"
1431 : /* no outputs */
1432 : "d" (__tmp),
1433 "M" (_SFR_MEM_ADDR(CLKPR)),
1434 "d" (__x)
1435 : "r0");
1436}
1437
1438/** \ingroup avr_power
1439\def clock_prescale_get()
1440Gets and returns the clock prescaler register setting. The return type is \c clock_div_t.
1441
1442\note For device with XTAL Divide Control Register (XDIV), return can actually
1443range from 1 to 129. Care should be taken has the return value could differ from the
1444typedef enum clock_div_t. This should only happen if clock_prescale_set was previously
1445called with a value other than those defined by \c clock_div_t.
1446*/
1447#define clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
1448
1449#elif defined(__AVR_ATmega16HVB__) \
1450|| defined(__AVR_ATmega16HVBREVB__) \
1451|| defined(__AVR_ATmega32HVB__) \
1452|| defined(__AVR_ATmega32HVBREVB__)
1453
1454typedef enum
1455{
1456 clock_div_1 = 0,
1457 clock_div_2 = 1,
1458 clock_div_4 = 2,
1459 clock_div_8 = 3
1460} clock_div_t;
1461
1462static __ATTR_ALWAYS_INLINE__ void clock_prescale_set(clock_div_t);
1463
1464void clock_prescale_set(clock_div_t __x)
1465{
1466 uint8_t __tmp = _BV(CLKPCE);
1467 __asm__ __volatile__ (
1468 "in __tmp_reg__,__SREG__" "\n\t"
1469 "cli" "\n\t"
1470 "sts %1, %0" "\n\t"
1471 "sts %1, %2" "\n\t"
1472 "out __SREG__, __tmp_reg__"
1473 : /* no outputs */
1474 : "d" (__tmp),
1475 "M" (_SFR_MEM_ADDR(CLKPR)),
1476 "d" (__x)
1477 : "r0");
1478}
1479
1480#define clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)))
1481
1482#elif defined(__AVR_ATA5790__) \
1483|| defined (__AVR_ATA5795__)
1484
1485typedef enum
1486{
1487 clock_div_1 = 0,
1488 clock_div_2 = 1,
1489 clock_div_4 = 2,
1490 clock_div_8 = 3,
1491 clock_div_16 = 4,
1492 clock_div_32 = 5,
1493 clock_div_64 = 6,
1494 clock_div_128 = 7,
1495} clock_div_t;
1496
1497static __ATTR_ALWAYS_INLINE__ void system_clock_prescale_set(clock_div_t);
1498
1499void system_clock_prescale_set(clock_div_t __x)
1500{
1501 uint8_t __tmp = _BV(CLKPCE);
1502 __asm__ __volatile__ (
1503 "in __tmp_reg__,__SREG__" "\n\t"
1504 "cli" "\n\t"
1505 "out %1, %0" "\n\t"
1506 "out %1, %2" "\n\t"
1507 "out __SREG__, __tmp_reg__"
1508 : /* no outputs */
1509 : "d" (__tmp),
1510 "I" (_SFR_IO_ADDR(CLKPR)),
1511 "d" (__x)
1512 : "r0");
1513}
1514
1515#define system_clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)))
1516
1517typedef enum
1518{
1519 timer_clock_div_reset = 0,
1520 timer_clock_div_1 = 1,
1521 timer_clock_div_2 = 2,
1522 timer_clock_div_4 = 3,
1523 timer_clock_div_8 = 4,
1524 timer_clock_div_16 = 5,
1525 timer_clock_div_32 = 6,
1526 timer_clock_div_64 = 7
1527} timer_clock_div_t;
1528
1529static __ATTR_ALWAYS_INLINE__ void timer_clock_prescale_set(timer_clock_div_t);
1530
1531void timer_clock_prescale_set(timer_clock_div_t __x)
1532{
1533 uint8_t __t;
1534 __asm__ __volatile__ (
1535 "in __tmp_reg__,__SREG__" "\n\t"
1536 "cli" "\n\t"
1537 "in %[temp],%[clkpr]" "\n\t"
1538 "out %[clkpr],%[enable]" "\n\t"
1539 "andi %[temp],%[not_CLTPS]" "\n\t"
1540 "or %[temp], %[set_value]" "\n\t"
1541 "out %[clkpr],%[temp]" "\n\t"
1542 "out __SREG__,__tmp_reg__"
1543 : [temp] "=d" (__t)
1544 : [clkpr] "I" (_SFR_IO_ADDR(CLKPR)),
1545 [enable] "r" (_BV(CLKPCE)),
1546 [not_CLTPS] "M" (0xFF & (~ ((1 << CLTPS2) | (1 << CLTPS1) | (1 << CLTPS0)))),
1547 [set_value] "r" ((__x & 7) << 3)
1548 : "r0");
1549}
1550
1551#define timer_clock_prescale_get() (timer_clock_div_t)(CLKPR & (uint8_t)((1<<CLTPS0)|(1<<CLTPS1)|(1<<CLTPS2)))
1552
1553#elif defined(__AVR_ATA6285__) \
1554|| defined(__AVR_ATA6286__)
1555
1556typedef enum
1557{
1558 clock_div_1 = 0,
1559 clock_div_2 = 1,
1560 clock_div_4 = 2,
1561 clock_div_8 = 3,
1562 clock_div_16 = 4,
1563 clock_div_32 = 5,
1564 clock_div_64 = 6,
1565 clock_div_128 = 7
1566} clock_div_t;
1567
1568static __ATTR_ALWAYS_INLINE__ void system_clock_prescale_set(clock_div_t);
1569
1570void system_clock_prescale_set(clock_div_t __x)
1571{
1572 uint8_t __t;
1573 __asm__ __volatile__ (
1574 "in __tmp_reg__,__SREG__" "\n\t"
1575 "cli" "\n\t"
1576 "in %[temp],%[clpr]" "\n\t"
1577 "out %[clpr],%[enable]" "\n\t"
1578 "andi %[temp],%[not_CLKPS]" "\n\t"
1579 "or %[temp], %[set_value]" "\n\t"
1580 "out %[clpr],%[temp]" "\n\t"
1581 "out __SREG__,__tmp_reg__"
1582 : [temp] "=d" (__t)
1583 : [clpr] "I" (_SFR_IO_ADDR(CLKPR)),
1584 [enable] "r" _BV(CLPCE),
1585 [not_CLKPS] "M" (0xFF & (~ ((1 << CLKPS2) | (1 << CLKPS1) | (1 << CLKPS0)))),
1586 [set_value] "r" (__x & 7)
1587 : "r0");
1588}
1589
1590#define system_clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)))
1591
1592typedef enum
1593{
1594 timer_clock_div_reset = 0,
1595 timer_clock_div_1 = 1,
1596 timer_clock_div_2 = 2,
1597 timer_clock_div_4 = 3,
1598 timer_clock_div_8 = 4,
1599 timer_clock_div_16 = 5,
1600 timer_clock_div_32 = 6,
1601 timer_clock_div_64 = 7
1602} timer_clock_div_t;
1603
1604static __ATTR_ALWAYS_INLINE__ void timer_clock_prescale_set(timer_clock_div_t);
1605
1606void timer_clock_prescale_set(timer_clock_div_t __x)
1607{
1608 uint8_t __t;
1609 __asm__ __volatile__ (
1610 "in __tmp_reg__,__SREG__" "\n\t"
1611 "cli" "\n\t"
1612 "in %[temp],%[clpr]" "\n\t"
1613 "out %[clpr],%[enable]" "\n\t"
1614 "andi %[temp],%[not_CLTPS]" "\n\t"
1615 "or %[temp], %[set_value]" "\n\t"
1616 "out %[clpr],%[temp]" "\n\t"
1617 "out __SREG__,__tmp_reg__"
1618 : [temp] "=d" (__t)
1619 : [clpr] "I" (_SFR_IO_ADDR(CLKPR)),
1620 [enable] "r" (_BV(CLPCE)),
1621 [not_CLTPS] "M" (0xFF & (~ ((1 << CLTPS2) | (1 << CLTPS1) | (1 << CLTPS0)))),
1622 [set_value] "r" ((__x & 7) << 3)
1623 : "r0");
1624}
1625
1626#define timer_clock_prescale_get() (timer_clock_div_t)(CLKPR & (uint8_t)((1<<CLTPS0)|(1<<CLTPS1)|(1<<CLTPS2)))
1627
1628#elif defined(__AVR_ATtiny24__) \
1629|| defined(__AVR_ATtiny24A__) \
1630|| defined(__AVR_ATtiny44__) \
1631|| defined(__AVR_ATtiny44A__) \
1632|| defined(__AVR_ATtiny84__) \
1633|| defined(__AVR_ATtiny84A__) \
1634|| defined(__AVR_ATtiny25__) \
1635|| defined(__AVR_ATtiny45__) \
1636|| defined(__AVR_ATtiny85__) \
1637|| defined(__AVR_ATtiny261A__) \
1638|| defined(__AVR_ATtiny261__) \
1639|| defined(__AVR_ATtiny461__) \
1640|| defined(__AVR_ATtiny461A__) \
1641|| defined(__AVR_ATtiny861__) \
1642|| defined(__AVR_ATtiny861A__) \
1643|| defined(__AVR_ATtiny2313__) \
1644|| defined(__AVR_ATtiny2313A__) \
1645|| defined(__AVR_ATtiny4313__) \
1646|| defined(__AVR_ATtiny13__) \
1647|| defined(__AVR_ATtiny13A__) \
1648|| defined(__AVR_ATtiny43U__) \
1649
1650typedef enum
1651{
1652 clock_div_1 = 0,
1653 clock_div_2 = 1,
1654 clock_div_4 = 2,
1655 clock_div_8 = 3,
1656 clock_div_16 = 4,
1657 clock_div_32 = 5,
1658 clock_div_64 = 6,
1659 clock_div_128 = 7,
1660 clock_div_256 = 8
1661} clock_div_t;
1662
1663static __ATTR_ALWAYS_INLINE__ void clock_prescale_set(clock_div_t);
1664
1665void clock_prescale_set(clock_div_t __x)
1666{
1667 uint8_t __tmp = _BV(CLKPCE);
1668 __asm__ __volatile__ (
1669 "in __tmp_reg__,__SREG__" "\n\t"
1670 "cli" "\n\t"
1671 "out %1, %0" "\n\t"
1672 "out %1, %2" "\n\t"
1673 "out __SREG__, __tmp_reg__"
1674 : /* no outputs */
1675 : "d" (__tmp),
1676 "I" (_SFR_IO_ADDR(CLKPR)),
1677 "d" (__x)
1678 : "r0");
1679}
1680
1681
1682#define clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
1683
1684#elif defined(__AVR_ATtiny441__) \
1685|| defined(__AVR_ATtiny841__)
1686
1687typedef enum
1688{
1689 clock_div_1 = 0,
1690 clock_div_2 = 1,
1691 clock_div_4 = 2,
1692 clock_div_8 = 3,
1693 clock_div_16 = 4,
1694 clock_div_32 = 5,
1695 clock_div_64 = 6,
1696 clock_div_128 = 7,
1697 clock_div_256 = 8
1698} clock_div_t;
1699
1700static __ATTR_ALWAYS_INLINE__ void clock_prescale_set (clock_div_t);
1701
1702void clock_prescale_set (clock_div_t __x)
1703{
1704 __asm__ __volatile__ (
1705 "in __tmp_reg__,__SREG__" "\n\t"
1706 "cli" "\n\t"
1707 "sts %2, %3" "\n\t"
1708 "sts %1, %0" "\n\t"
1709 "out __SREG__, __tmp_reg__"
1710 : /* no outputs */
1711 : "r" (__x),
1712 "n" (_SFR_MEM_ADDR(CLKPR)),
1713 "n" (_SFR_MEM_ADDR(CCP)),
1714 "r" ((uint8_t) 0xD8)
1715 : "r0");
1716}
1717
1718#define clock_prescale_get() (clock_div_t) (CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
1719
1720#elif defined(__AVR_ATmega64__) \
1721|| defined(__AVR_ATmega103__) \
1722|| defined(__AVR_ATmega128__)
1723
1724//Enum is declared for code compatibility
1725typedef enum
1726{
1727 clock_div_1 = 1,
1728 clock_div_2 = 2,
1729 clock_div_4 = 4,
1730 clock_div_8 = 8,
1731 clock_div_16 = 16,
1732 clock_div_32 = 32,
1733 clock_div_64 = 64,
1734 clock_div_128 = 128
1735} clock_div_t;
1736
1737static __ATTR_ALWAYS_INLINE__ void clock_prescale_set(clock_div_t);
1738
1739void clock_prescale_set(clock_div_t __x)
1740{
1741 if((__x <= 0) || (__x > 129))
1742 {
1743 return;//Invalid value.
1744 }
1745 else
1746 {
1747 uint8_t __tmp = 0;
1748 //Algo explained:
1749 //1 - Clear XDIV in order for it to accept a new value (actually only
1750 // XDIVEN need to be cleared, but clearing XDIV is faster than
1751 // read-modify-write since we will rewrite XDIV later anyway)
1752 //2 - wait 8 clock cycle for stability, see datasheet errata
1753 //3 - Exit if requested prescaler is 1
1754 //4 - Calculate XDIV6..0 value = 129 - __x
1755 //5 - Set XDIVEN bit in calculated value
1756 //6 - write XDIV with calculated value
1757 //7 - wait 8 clock cycle for stability, see datasheet errata
1758 __asm__ __volatile__ (
1759 "in __tmp_reg__,__SREG__" "\n\t"
1760 "cli" "\n\t"
1761 "out %2, __zero_reg__" "\n\t"
1762 "nop" "\n\t"
1763 "nop" "\n\t"
1764 "nop" "\n\t"
1765 "nop" "\n\t"
1766 "nop" "\n\t"
1767 "nop" "\n\t"
1768 "nop" "\n\t"
1769 "nop" "\n\t"
1770 "cpi %1, 0x01" "\n\t"
1771 "breq L_%=" "\n\t"
1772 "ldi %0, 0x81" "\n\t" //129
1773 "sub %0, %1" "\n\t"
1774 "ori %0, 0x80" "\n\t" //128
1775 "out %2, %0" "\n\t"
1776 "nop" "\n\t"
1777 "nop" "\n\t"
1778 "nop" "\n\t"
1779 "nop" "\n\t"
1780 "nop" "\n\t"
1781 "nop" "\n\t"
1782 "nop" "\n\t"
1783 "nop" "\n\t"
1784 "L_%=: " "out __SREG__, __tmp_reg__"
1785 : "=d" (__tmp)
1786 : "d" (__x),
1787 "I" (_SFR_IO_ADDR(XDIV))
1788 : "r0");
1789 }
1790}
1791
1792static __ATTR_ALWAYS_INLINE__ clock_div_t clock_prescale_get(void);
1793
1794clock_div_t clock_prescale_get(void)
1795{
1796 if (bit_is_clear(XDIV, XDIVEN))
1797 {
1798 return 1;
1799 }
1800 else
1801 {
1802 return (clock_div_t) (129 - (XDIV & 0x7F));
1803 }
1804}
1805
1806#elif defined(__AVR_ATtiny4__) \
1807|| defined(__AVR_ATtiny5__) \
1808|| defined(__AVR_ATtiny9__) \
1809|| defined(__AVR_ATtiny10__) \
1810|| defined(__AVR_ATtiny102__) \
1811|| defined(__AVR_ATtiny104__) \
1812|| defined(__AVR_ATtiny20__) \
1813|| defined(__AVR_ATtiny40__) \
1814
1815typedef enum
1816{
1817 clock_div_1 = 0,
1818 clock_div_2 = 1,
1819 clock_div_4 = 2,
1820 clock_div_8 = 3,
1821 clock_div_16 = 4,
1822 clock_div_32 = 5,
1823 clock_div_64 = 6,
1824 clock_div_128 = 7,
1825 clock_div_256 = 8
1826} clock_div_t;
1827
1828static __ATTR_ALWAYS_INLINE__ void clock_prescale_set(clock_div_t);
1829
1830void clock_prescale_set(clock_div_t __x)
1831{
1832 uint8_t __tmp = 0xD8;
1833 __asm__ __volatile__ (
1834 "in __tmp_reg__,__SREG__" "\n\t"
1835 "cli" "\n\t"
1836 "out %1, %0" "\n\t"
1837 "out %2, %3" "\n\t"
1838 "out __SREG__, __tmp_reg__"
1839 : /* no outputs */
1840 : "d" (__tmp),
1841 "I" (_SFR_IO_ADDR(CCP)),
1842 "I" (_SFR_IO_ADDR(CLKPSR)),
1843 "d" (__x)
1844 : "r16");
1845}
1846
1847#define clock_prescale_get() (clock_div_t)(CLKPSR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
1848
1849#endif
1850
1851#endif /* _AVR_POWER_H_ */
#define clock_prescale_get()
Definition: power.h:1447
static void power_all_enable()
static void power_all_disable()
void clock_prescale_set(clock_div_t __x)
Definition: power.h:1422
#define _BV(bit)
Definition: sfr_defs.h:208
#define bit_is_clear(sfr, bit)
Definition: sfr_defs.h:245
unsigned char uint8_t
Definition: stdint.h:83