99#define wdt_reset() __asm__ __volatile__ ("wdr")
103#ifndef __ATTR_ALWAYS_INLINE__
104#define __ATTR_ALWAYS_INLINE__ __inline__ __attribute__((__always_inline__))
108# define _WD_PS3_MASK _BV(WDP3)
110# define _WD_PS3_MASK 0x00
114# define _WD_CONTROL_REG WDTCSR
116# define _WD_CONTROL_REG WDTCR
118# define _WD_CONTROL_REG WDT
122#define _WD_CHANGE_BIT WDTOE
124#define _WD_CHANGE_BIT WDCE
140#define wdt_enable(timeout)
144#if defined(__AVR_XMEGA__)
146#if defined (WDT_CTRLA) && !defined(RAMPD)
148#define wdt_enable(timeout) \
151__asm__ __volatile__ ( \
153 "out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \
154 "lds %[tmp], %[wdt_reg]" "\n\t" \
155 "sbr %[tmp], %[wdt_enable_timeout]" "\n\t" \
156 "sts %[wdt_reg], %[tmp]" "\n\t" \
157 "1:lds %[tmp], %[wdt_status_reg]" "\n\t" \
158 "sbrc %[tmp], %[wdt_syncbusy_bit]" "\n\t" \
160 : [tmp] "=d" (__temp) \
161 : [ccp_reg] "I" (_SFR_IO_ADDR(CCP)), \
162 [ioreg_cen_mask] "r" ((uint8_t)CCP_IOREG_gc), \
163 [wdt_reg] "n" (_SFR_MEM_ADDR(WDT_CTRLA)), \
164 [wdt_enable_timeout] "M" (timeout), \
165 [wdt_status_reg] "n" (_SFR_MEM_ADDR(WDT_STATUS)), \
166 [wdt_syncbusy_bit] "I" (WDT_SYNCBUSY_bm) \
170#define wdt_disable() \
173__asm__ __volatile__ ( \
175 "out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \
176 "lds %[tmp], %[wdt_reg]" "\n\t" \
177 "cbr %[tmp], %[timeout_mask]" "\n\t" \
178 "sts %[wdt_reg], %[tmp]" \
179 : [tmp] "=d" (__temp) \
180 : [ccp_reg] "I" (_SFR_IO_ADDR(CCP)), \
181 [ioreg_cen_mask] "r" ((uint8_t)CCP_IOREG_gc), \
182 [wdt_reg] "n" (_SFR_MEM_ADDR(WDT_CTRLA)),\
183 [timeout_mask] "I" (WDT_PERIOD_gm) \
201#define wdt_enable(timeout) \
204__asm__ __volatile__ ( \
205 "in __tmp_reg__, %[rampd]" "\n\t" \
206 "out %[rampd], __zero_reg__" "\n\t" \
207 "out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \
208 "sts %[wdt_reg], %[wdt_enable_timeout]" "\n\t" \
209 "1:lds %[tmp], %[wdt_status_reg]" "\n\t" \
210 "sbrc %[tmp], %[wdt_syncbusy_bit]" "\n\t" \
212 "out %[rampd], __tmp_reg__" \
213 : [tmp] "=r" (__temp) \
214 : [rampd] "I" (_SFR_IO_ADDR(RAMPD)), \
215 [ccp_reg] "I" (_SFR_IO_ADDR(CCP)), \
216 [ioreg_cen_mask] "r" ((uint8_t)CCP_IOREG_gc), \
217 [wdt_reg] "n" (_SFR_MEM_ADDR(WDT_CTRL)), \
218 [wdt_enable_timeout] "r" ((uint8_t)(WDT_CEN_bm | WDT_ENABLE_bm | timeout)), \
219 [wdt_status_reg] "n" (_SFR_MEM_ADDR(WDT_STATUS)), \
220 [wdt_syncbusy_bit] "I" (WDT_SYNCBUSY_bm) \
225#define wdt_disable() \
226__asm__ __volatile__ ( \
227 "in __tmp_reg__, %[rampd]" "\n\t" \
228 "out %[rampd], __zero_reg__" "\n\t" \
229 "out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \
230 "sts %[wdt_reg], %[disable_mask]" "\n\t" \
231 "out %[rampd], __tmp_reg__" \
233 : [rampd] "I" (_SFR_IO_ADDR(RAMPD)), \
234 [ccp_reg] "I" (_SFR_IO_ADDR(CCP)), \
235 [ioreg_cen_mask] "r" ((uint8_t)CCP_IOREG_gc), \
236 [wdt_reg] "n" (_SFR_MEM_ADDR(WDT_CTRL)), \
237 [disable_mask] "r" ((uint8_t)((~WDT_ENABLE_bm) | WDT_CEN_bm)) \
243#elif defined(__AVR_TINY__)
245#define wdt_enable(value) \
246__asm__ __volatile__ ( \
247 "in __tmp_reg__,__SREG__" "\n\t" \
250 "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" \
251 "out %[WDTREG],%[WDVALUE]" "\n\t" \
252 "out __SREG__,__tmp_reg__" \
254 : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), \
255 [SIGNATURE] "r" ((uint8_t)0xD8), \
256 [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
257 [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) \
258 | _BV(WDE) | (value & 0x07) )) \
262#define wdt_disable() \
265__asm__ __volatile__ ( \
266 "in __tmp_reg__,__SREG__" "\n\t" \
269 "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" \
270 "in %[TEMP_WD],%[WDTREG]" "\n\t" \
271 "cbr %[TEMP_WD],%[WDVALUE]" "\n\t" \
272 "out %[WDTREG],%[TEMP_WD]" "\n\t" \
273 "out __SREG__,__tmp_reg__" \
274 : [TEMP_WD] "=d" (__temp_wd) \
275 : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), \
276 [SIGNATURE] "r" ((uint8_t)0xD8), \
277 [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
278 [WDVALUE] "n" (1 << WDE) \
285static __ATTR_ALWAYS_INLINE__
288 if (!_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P (_WD_CONTROL_REG))
290 __asm__ __volatile__ (
291 "in __tmp_reg__,__SREG__" "\n\t"
294 "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t"
295 "sts %[WDTREG],%[WDVALUE]" "\n\t"
296 "out __SREG__,__tmp_reg__"
298 : [CCPADDRESS]
"n" (_SFR_MEM_ADDR(CCP)),
299 [SIGNATURE]
"r" ((
uint8_t)0xD8),
300 [WDTREG]
"n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
301 [WDVALUE]
"r" ((
uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00)
302 |
_BV(WDE) | (value & 0x07) ))
306 else if (!_SFR_IO_REG_P (CCP) && _SFR_IO_REG_P (_WD_CONTROL_REG))
308 __asm__ __volatile__ (
309 "in __tmp_reg__,__SREG__" "\n\t"
312 "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t"
313 "out %[WDTREG],%[WDVALUE]" "\n\t"
314 "out __SREG__,__tmp_reg__"
316 : [CCPADDRESS]
"n" (_SFR_MEM_ADDR(CCP)),
317 [SIGNATURE]
"r" ((
uint8_t)0xD8),
318 [WDTREG]
"I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
319 [WDVALUE]
"r" ((
uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00)
320 |
_BV(WDE) | (value & 0x07) ))
324 else if (_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P (_WD_CONTROL_REG))
326 __asm__ __volatile__ (
327 "in __tmp_reg__,__SREG__" "\n\t"
330 "out %[CCPADDRESS],%[SIGNATURE]" "\n\t"
331 "sts %[WDTREG],%[WDVALUE]" "\n\t"
332 "out __SREG__,__tmp_reg__"
334 : [CCPADDRESS]
"I" (_SFR_IO_ADDR(CCP)),
335 [SIGNATURE]
"r" ((
uint8_t)0xD8),
336 [WDTREG]
"n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
337 [WDVALUE]
"r" ((
uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00)
338 |
_BV(WDE) | (value & 0x07) ))
344 __asm__ __volatile__ (
345 "in __tmp_reg__,__SREG__" "\n\t"
348 "out %[CCPADDRESS],%[SIGNATURE]" "\n\t"
349 "out %[WDTREG],%[WDVALUE]" "\n\t"
350 "out __SREG__,__tmp_reg__"
352 : [CCPADDRESS]
"I" (_SFR_IO_ADDR(CCP)),
353 [SIGNATURE]
"r" ((
uint8_t)0xD8),
354 [WDTREG]
"I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
355 [WDVALUE]
"r" ((
uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00)
356 |
_BV(WDE) | (value & 0x07) ))
362static __ATTR_ALWAYS_INLINE__
363void wdt_disable (
void)
365 if (!_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P(_WD_CONTROL_REG))
368 __asm__ __volatile__ (
369 "in __tmp_reg__,__SREG__" "\n\t"
372 "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t"
373 "lds %[TEMP_WD],%[WDTREG]" "\n\t"
374 "cbr %[TEMP_WD],%[WDVALUE]" "\n\t"
375 "sts %[WDTREG],%[TEMP_WD]" "\n\t"
376 "out __SREG__,__tmp_reg__"
377 : [TEMP_WD]
"=d" (__temp_wd)
378 : [CCPADDRESS]
"n" (_SFR_MEM_ADDR(CCP)),
379 [SIGNATURE]
"r" ((
uint8_t)0xD8),
380 [WDTREG]
"n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
381 [WDVALUE]
"n" (1 << WDE)
385 else if (!_SFR_IO_REG_P (CCP) && _SFR_IO_REG_P(_WD_CONTROL_REG))
388 __asm__ __volatile__ (
389 "in __tmp_reg__,__SREG__" "\n\t"
392 "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t"
393 "in %[TEMP_WD],%[WDTREG]" "\n\t"
394 "cbr %[TEMP_WD],%[WDVALUE]" "\n\t"
395 "out %[WDTREG],%[TEMP_WD]" "\n\t"
396 "out __SREG__,__tmp_reg__"
397 : [TEMP_WD]
"=d" (__temp_wd)
398 : [CCPADDRESS]
"n" (_SFR_MEM_ADDR(CCP)),
399 [SIGNATURE]
"r" ((
uint8_t)0xD8),
400 [WDTREG]
"I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
401 [WDVALUE]
"n" (1 << WDE)
405 else if (_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P(_WD_CONTROL_REG))
408 __asm__ __volatile__ (
409 "in __tmp_reg__,__SREG__" "\n\t"
412 "out %[CCPADDRESS],%[SIGNATURE]" "\n\t"
413 "lds %[TEMP_WD],%[WDTREG]" "\n\t"
414 "cbr %[TEMP_WD],%[WDVALUE]" "\n\t"
415 "sts %[WDTREG],%[TEMP_WD]" "\n\t"
416 "out __SREG__,__tmp_reg__"
417 : [TEMP_WD]
"=d" (__temp_wd)
418 : [CCPADDRESS]
"I" (_SFR_IO_ADDR(CCP)),
419 [SIGNATURE]
"r" ((
uint8_t)0xD8),
420 [WDTREG]
"n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
421 [WDVALUE]
"n" (1 << WDE)
428 __asm__ __volatile__ (
429 "in __tmp_reg__,__SREG__" "\n\t"
432 "out %[CCPADDRESS],%[SIGNATURE]" "\n\t"
433 "in %[TEMP_WD],%[WDTREG]" "\n\t"
434 "cbr %[TEMP_WD],%[WDVALUE]" "\n\t"
435 "out %[WDTREG],%[TEMP_WD]" "\n\t"
436 "out __SREG__,__tmp_reg__"
437 : [TEMP_WD]
"=d" (__temp_wd)
438 : [CCPADDRESS]
"I" (_SFR_IO_ADDR(CCP)),
439 [SIGNATURE]
"r" ((
uint8_t)0xD8),
440 [WDTREG]
"I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
441 [WDVALUE]
"n" (1 << WDE)
449static __ATTR_ALWAYS_INLINE__
452 if (_SFR_IO_REG_P (_WD_CONTROL_REG))
454 __asm__ __volatile__ (
455 "in __tmp_reg__,__SREG__" "\n\t"
459 "out __SREG__,__tmp_reg__" "\n\t"
462 :
"I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
464 "r" ((
uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
465 _BV(WDE) | (value & 0x07)) )
471 __asm__ __volatile__ (
472 "in __tmp_reg__,__SREG__" "\n\t"
476 "out __SREG__,__tmp_reg__" "\n\t"
479 :
"n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
481 "r" ((
uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
482 _BV(WDE) | (value & 0x07)) )
488static __ATTR_ALWAYS_INLINE__
489void wdt_disable (
void)
491 if (_SFR_IO_REG_P (_WD_CONTROL_REG))
494 __asm__ __volatile__ (
495 "in __tmp_reg__,__SREG__" "\n\t"
498 "in %[TEMPREG],%[WDTREG]" "\n\t"
499 "ori %[TEMPREG],%[WDCE_WDE]" "\n\t"
500 "out %[WDTREG],%[TEMPREG]" "\n\t"
501 "out %[WDTREG],__zero_reg__" "\n\t"
502 "out __SREG__,__tmp_reg__"
503 : [TEMPREG]
"=d" (__temp_reg)
504 : [WDTREG]
"I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
512 __asm__ __volatile__ (
513 "in __tmp_reg__,__SREG__" "\n\t"
516 "lds %[TEMPREG],%[WDTREG]" "\n\t"
517 "ori %[TEMPREG],%[WDCE_WDE]" "\n\t"
518 "sts %[WDTREG],%[TEMPREG]" "\n\t"
519 "sts %[WDTREG],__zero_reg__" "\n\t"
520 "out __SREG__,__tmp_reg__"
521 : [TEMPREG]
"=d" (__temp_reg)
522 : [WDTREG]
"n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
583#if defined(__DOXYGEN__) || defined(WDP3)
#define _BV(bit)
Definition: sfr_defs.h:208
unsigned char uint8_t
Definition: stdint.h:83
#define wdt_enable(timeout)
Definition: wdt.h:140