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#define clock_prescale_get |
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(clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3))) |
Gets and returns the clock prescaler register setting. The return type is clock_div_t
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- Note
- For device with XTAL Divide Control Register (XDIV), return can actually range from 1 to 129. Care should be taken has the return value could differ from the typedef enum clock_div_t. This should only happen if clock_prescale_set was previously called with a value other than those defined by
clock_div_t
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static __inline void __attribute__ |
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(__always_inline__) |
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